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SPRUG18 Datasheet(PDF) 170 Page - Texas Instruments |
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SPRUG18 Datasheet(HTML) 170 Page - Texas Instruments |
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170 / 214 page  TMS320C6474 SPRS552H – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com 7.17 Enhanced Turbo Decoder Coprocessor (TCP2) 7.17.1 TCP2 Device-Specific Information The C6474 device has a high-performance embedded coprocessor Turbo-Decoder Coprocessor (TCP2) that significantly speeds up channel-decoding operations on-chip. The TCP2 operating at CPU clock divided-by-3 can decode up to fifty 384-Kbps or eight 2-Mbps turbo-encoded channels (assuming 6 iterations). The TCP2 implements the max* log-map algorithm and is designed to support all polynomials and rates required by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable frame length and turbo interleaver. Decoding parameters such as the number of iterations and stopping criteria are also programmable. Communications between the TCP2 and the CPU are carried out through the EDMA3 controller. The TCP2 supports: • Parallel concatenated convolutional turbo decoding using the MAP algorithm • All turbo code rates greater than or equal to 1/5 • 3GPP and CDMA2000 turbo encoder trellis • 3GPP and CDMA2000 block sizes in standalone mode • Larger block sizes in shared processing mode • Both max log MAP and log MAP decoding • Sliding windows algorithm with variable reliability and prolog lengths • The prolog reduction algorithm • Execution of a minimum and maximum number of iterations • The SNR stopping criteria algorithm • The CRC stopping criteria algorithm For more detailed information on the TCP2, see the TMS320C6474 DSP Turbo-Decoder Coprocessor 2 (TCP2) Reference Guide (literature number SPRUG21). 7.17.2 TCP2 Peripheral Register Description(s) Table 7-78. TCP2 Registers EDMA BUS HEX ADDRESS RANGE CONFIGURATION BUS HEX ACRONYM REGISTER NAME ADDRESS RANGE 5000 0000 - TCPIC0 TCP2 Input Configuration Register 0 5000 0004 - TCPIC1 TCP2 Input Configuration Register 1 5000 0008 - TCPIC2 TCP2 Input Configuration Register 2 5000 000C - TCPIC3 TCP2 Input Configuration Register 3 5000 0010 - TCPIC4 TCP2 Input Configuration Register 4 5000 0014 - TCPIC5 TCP2 Input Configuration Register 5 5000 0018 - TCPIC6 TCP2 Input Configuration Register 6 5000 001C - TCPIC7 TCP2 Input Configuration Register 7 5000 0020 - TCPIC8 TCP2 Input Configuration Register 8 5000 0024 - TCPIC9 TCP2 Input Configuration Register 9 5000 0028 - TCPIC10 TCP2 Input Configuration Register 10 5000 002C - TCPIC11 TCP2 Input Configuration Register 11 5000 0030 - TCPIC12 TCP2 Input Configuration Register 12 5000 0034 - TCPIC13 TCP2 Input Configuration Register 13 5000 0038 - TCPIC14 TCP2 Input Configuration Register 14 5000 003C - TCPIC15 TCP2 Input Configuration Register 15 5000 0040 - TCPOUT0 TCP2 Output Parameters Register 0 5000 0044 - TCPOUT1 TCP2 Output Parameters Register 1 170 Peripheral Information and Electrical Specifications Copyright © 2008–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) :TMS320C6474 |
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