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DAC3174 Datasheet(PDF) 13 Page - Texas Instruments |
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DAC3174 Datasheet(HTML) 13 Page - Texas Instruments |
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13 / 40 page ![]() DAC3174 www.ti.com SLAS837A – APRIL 2013 – REVISED MAY 2013 ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS (continued) Typical values at T A = 25°C, full temperature range is T MIN = –40°C to T MAX = 85°C, DAC sample rate = 500MSPS, 50% clock duty cycle, VDDA33/IOVDD = 3.3V, VDDA18/CLKVDD18/DIGVDD18 = 1.8V, IOUT FS = 20mA (unless otherwise noted). PARAMETERS NOTES MIN TYP MAX UNITS LVDS INPUT TIMING config3 Setting datadly clkdly 0 0 -20 0 1 -120 0 2 -220 0 3 -310 D[x..0] valid to DATACLK rising or falling edge for single bus single clock mode ; 0 4 -390 _ 0 5 -480 DA/DB[x…0] valid to DB_CLK rising or falling ts(DATA) Setup time edge for dual bus single clock mode; 0 6 -560 ps _ 0 7 -630 DA[x..0] valid to DA_CLK rising or falling edge, 1 0 70 and DB[x…0] valid for DB_CLK rising or falling edge for dual bus dual clock mode 2 0 150 3 0 230 4 0 330 5 0 430 6 0 530 7 0 620 congfig3 Setting datadly clkdly 0 0 310 0 1 390 0 2 480 0 3 560 D[x..0] valid to DATACLK rising or falling edge for single bus single clock mode; 0 4 650 _ 0 5 740 DA/DB[x…0] valid to DB_CLK rising or falling th(DATA) Hold time edge for dual bus single clock mode; 0 6 850 ps _ 0 7 930 DA[x..0] valid to DA_CLK rising or falling edge, 1 0 200 and DB[x…0] valid for DB_CLK rising or falling edge for dual bus dual clock mode. 2 0 100 3 0 20 4 0 -60 5 0 -140 6 0 -220 7 0 -290 Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links :DAC3174 |
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