rwb

A6

A5

A4

A3

A2

A1

A0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Instruction Cycle

Data Transfer Cycle

tS (SDENB)

tS(SDIO) tH(SDIO)

t

SCLK

SDENB

SCLK

SDIO

SDENB

SCLK

SDIO

DAC3174

SLAS837A – APRIL 2013 – REVISED MAY 2013

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SERIAL INTERFACE DESCRIPTION

The serial port of the DAC3174 is a flexible serial interface which communicates with industry standard

microprocessors and microcontrollers. The interface provides read/write access to all registers used to define the

operating modes of DAC3174. It is compatible with most synchronous transfer formats and can be configured as

a 3 or 4 pin interface by sif4_ena in register config 0, bit 9. In both configurations, SCLK is the serial interface

input clock and SDENB is serial interface enable. For 3 pin configuration, SDIO is a bidirectional pin for both data

in and data out. For 4 pin configuration, SDIO is data in only and SDO is data out only. Data is input into the

device with the rising edge of SCLK. Data is output from the device on the falling edge of SCLK.

Each read/write operation is framed by signal SDENB (Serial Data Enable Bar) asserted low. The first frame byte

is the instruction cycle which identifies the following data transfer cycle as read or write as well as the 7-bit

address to be accessed. Table 5 indicates the function of each bit in the instruction cycle and is followed by a

detailed description of each bit. The data transfer cycle consists of two bytes.

Table 5. Instruction byte of the Serial interface

MSB

LSB

Bit

7

6

5

4

3

2

1

0

Description

R/W

A6

A5

A4

A3

A2

A1

A0

R/W

Identifies the following data transfer cycle as a read or write operation. A high indicates a read

operation from DAC3174 and a low indicates a write operation to DAC3174.

[A6 : A0]

Identifies the address of the register to be accessed during the read or write operation.

Figure 27 shows the serial interface timing diagram for a DAC3174 write operation. SCLK is the serial interface

clock input to DAC3174. Serial data enable SDENB is an active low input to DAC3174. SDIO is serial data in.

Input data to DAC3174 is clocked on the rising edges of SCLK.

Figure 27. Serial Interface Write Timing Diagram

Figure 28 shows the serial interface timing diagram for a DAC3174 read operation. SCLK is the serial interface

clock input to DAC3174. Serial data enable SDENB is an active low input to DAC3174. SDIO is serial data in

during the instruction cycle. In 3 pin configuration, SDIO is data out from the DAC3174 during the data transfer

cycle, while SDO is in a high-impedance state. In 4 pin configuration, both SDIO and SDO are data out from the

DAC3174 during the data transfer cycle. At the end of the data transfer, SDIO and SDO will output low on the

final falling edge of SCLK until the rising edge of SDENB when they will 3-state.

22

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