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DAC3174 Datasheet(PDF) 21 Page - Texas Instruments |
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DAC3174 Datasheet(HTML) 21 Page - Texas Instruments |
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21 / 40 page  DAC3174 www.ti.com SLAS837A – APRIL 2013 – REVISED MAY 2013 Table 3. Mode: Dual Bus Single Clock Mode DIFFERENTIAL PAIR (P/N) DB_CLK RISING EDGE DB_CLK FALLING EDGE DA6 A13 A6 DA5 A12 A5 DA4 A11 A4 DA3 A10 A3 DA2 A9 A2 DA1 A8 A1 DA0 A7 A0 DB6 B13 B6 DB5 B12 B5 DB4 B11 B4 DB3 B10 B3 DB2 B9 B2 DB1 B8 B1 DB0 B7 B0 SYNC FIFO Write Reset - Table 4. Mode: Dual Bus Dual Clock Mode DIFFERENTIAL PAIR (P/N) DA_CLK RISING EDGE DA_CLK FALLING EDGE DA6 A13 A6 DA5 A12 A5 DA4 A11 A4 DA3 A10 A3 DA2 A9 A2 DA1 A8 A1 DA0 A7 A0 DB_CLK RISING EDGE DB_CLK FALLING EDGE DB6 B13 B6 DB5 B12 B5 DB4 B11 B4 DB3 B10 B3 DB2 B9 B2 DB1 B8 B1 DB0 B7 B0 . NOTE When the register rev (config0, bit 11) is asserted, the MSB/LSB of the input bits are reversed. When using the 14-bit interface, all 14 bits are reversed as one word; when using the 7-bit interface, each 7-bit is reversed. Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Links :DAC3174 |
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