DAC3174 datasheet(33/40 Pages) TI

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DAC3174

www.ti.com

SLAS837A – APRIL 2013 – REVISED MAY 2013

Addr

Bit

Name

Function

Default Value

Name

(Hex)

config25

0x19

15:0

fa002_ data(63:48)

Upper 16bits of the DIE ID word

READ

ONLY

Addr

Default

Bit

Name

Function

Name

(Hex)

Value

config127

0x7F

15:14

reserved

READ

13:12

reserved

ONLY/No

11:10

reserved

RESET

Value

9:8

reserved

titest_voh

A fixed ‘1’ that can be used to test the Voh at the SIF output.

titest_vol

A fixed ‘0’ that can be used to test the Vol at the SIF output.

4:3

vendorid

Fixed at 01

2:0

versionid

Chip version

001

Synchronization Modes

There are three modes of syncing included in the DAC3174.

•

NORMAL Dual Sync – The SYNC pin is used to align the input side of the FIFO (write pointers) with the A(0)

sample. The ALIGN pin is used to reset the output side of the FIFO (read pointers) to the offset value.

Multiple chip alignment can be accomplished with this kind of syncing.

•

SYNC ONLY – In this mode only the SYNC pin is used to sync both the read and write pointers of the FIFO.

There is an asynchronized handoff between the DATACLK and DACCLK when using this mode, therefore it is

impossible to accurately align multiple chips closer than 2 or 3T.

•

SIF_SYNC – When neither SYNC nor ALIGN are used, a programmable SYNC pulse can be used to sync

the design. However, the same issues as SYNC ONLY apply. There is an asynchronized handoff between

the serial clock domain and the two sides of the FIFO. Because of the asynchronous nature of the SIF_SYNC

it is impossible to align the sync up with any sample at the input. NOTE: SIF_SYNC mode is the only

synchronization mode supported in dual bus mode.

NOTE

When ALIGNP/N are not used, it is recommended to clear the alignrx_ena register

(config1, bit 4), and tie ALIGNP to DIGVDD18 and ALIGNN to GROUND. When SYNCP/N

are not used, it is recommended to clear register syncrx_ena (config0, bit3), and the

unused SYNCP/N pins can be left open or tied to GROUND.

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