DAC3174 datasheet(27/40 Pages) TI

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DAC3174

www.ti.com

SLAS837A – APRIL 2013 – REVISED MAY 2013

Addr

Bit

Name

Function

Default Value

Name

(Hex)

config3

0x03

15:13

datadlya

Controls the delay of the A data inputs through the LVDS receivers. 000

0= no additional delay and each LSB adds a nominal 80ps.

12:10

clkdlya

Controls the delay of the A data clock input through the LVDS

000

receivers. 0= no additional delay and each LSB adds a nominal

80ps.

9:7

datadlyb

Controls the delay of the B data inputs through the LVDS receivers. 000

0= no additional delay and each LSB adds a nominal 80ps.

6:4

clkdlyb

Controls the delay of the B data clock input through the LVDS

000

receivers. 0= no additional delay and each LSB adds a nominal

80ps.

extref_ ena

Enables external reference for the DAC when set.

2:1

reserved

dual_ clock_ena

When asserted it tells the LVDS input circuit that there are two

individual data clocks. NOTE: must be in SIF_SYNC mode.

Addr

Default

Bit

Name

Function

Name

(Hex)

Value

config4

0x04

15:14

reserved

WRITE TO

13:0

iotest_ results

The values of these bits tell which bit in the input word failed during the

0x0000

CLEAR/

io-test pattern comparison. 13:7 match up with the 7 bits from port A

No RESET

and 6:0 match up with bits from port B.

value

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