DAC5682 datasheet(34/49 Pages) TI

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BBOUT Clk

Ideal

Data

Placement

Ideal

Data

Placement

BBOUT Data, BBOUT Sync

skmin

skmax

skmin

T0509-01

GC5330

GC5337

SLWS226 B

– DECEMBER 2010 – REVISED JANUARY 2011

www.ti.com

Figure 17. RX Baseband LVDS DDR0 Output Timing Specifications

The DAC TX interface has a 40-signal output bus. The DAC TX bus can provide 4-byte-wide or 2-word-wide

interfaces. Table 5 shows the different DAC devices that can be connected to the TX output ports. The DAC TX

interface has two styles of clock output, one where the DDR clock is centered over the output data-stable time,

and one where the clock transition is aligned with the data transition. If the output clock rate is greater than

500 MHz, the GC533x must be configured for clock transition aligned with the data transition. Depending on the

DAC type selected, the clock, frame, and data for the DAC may require a trace routing delay for proper

alignment. See Table 14, Table 15, and Table 16.

Table 14. TX DAC and Envelope Modulator Characteristics

DAC or Envelope Modulator

Timing Model

DAC Data Rate

Table Number

Figure Number

Type

DAC3282, 3283 byte-envelope

Clock centered over data

<1000 Mbyte/s

Table 15

Figure 18

modulator

DAC3282, 3283 byte-envelope

Clock aligned with data at GC533x, routing

≥1000 Mbyted/s

Table 16

Figure 19

modulator

provides timing skew for clock centered over data

DAC3484, 3482 word

Clock centered over data

<1000 Mword/s

Table 15

Figure 18

Clock aligned with data at GC533x, routing

DAC3484, 3482 word

≥1000 Mword/s

Table 16

Figure 19

provides timing skew for clock centered over data

Clock aligned with data at GC533x. PC board

DAC5682

routing may be required to provide some timing

All

Table 16

Figure 19

skew for optimum performance.

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