DAC5682 datasheet(40/49 Pages) TI

40 / 49 page

SYNCA, SYNCB

DPD Clock

T0514-01

4 cycles, min.

DPDClock

SyncOut

T0515-01

GC5330

GC5337

SLWS226 B

– DECEMBER 2010 – REVISED JANUARY 2011

www.ti.com

Figure 22. SYNCA, SYNCB Timing to DPD Clock

Table 23. DPD Clock and Sync Out Switching Characteristics

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

td(SYNCOut)

Data valid after DPD clock

See (1)

0.95

tHO(SYNCOut)

Data held valid after next DPD clock

See (1)

0.3

(1)

Chip specifications are production tested at 90

°C case temperature for the given specification. Early production lots are sample tested

–40°C.

Figure 23. Sync Out Timing to DPD Clock

The JTAG test connections are used with the CMOS signals for board interconnection tests. The TRSTB pin

must be toggled low, or low initially. If JTAG is not used, the TRSTB signal should be GROUNDed or tied to

GND through

< 1 kΩ resistance. TRSTB should be 0 for normal operation.

Table 24. JTAG Switching Characteristics

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

fTCK

JTAG clock frequency

MHz

tTCKL

JTAG clock low period

See (1)

tTCKH

JTAG clock high period

See (1)

tsu(TDI,TMS)

Input data setup time before fTCK↑

See (1)

tH(TDI,TMS)

Input data hold time after fTCK↑

See (1)

1.5

Output data delay from fTCK↓

See (1)

tOHD(TDO)

Previous data valid from fTCK↓

See (1)

(1)

Chip specifications are production tested at 90

°C case temperature for the given specification. Early production lots are sample tested

–40°C.

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