DAC5682 datasheet(37/49 Pages) TI

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ADC Data

ADC Clock

T0512-01

GC5330

GC5337

www.ti.com

SLWS226 B

– DECEMBER 2010 – REVISED JANUARY 2011

Table 17. General LVDS ADC Interface Table

Clock

ADC Type

Bits per Rail

ADC Format

ADC Input Timing Table

ADC Figure

Centered

ADS5400

Yes

Table 18

Figure 20

ADS54RF63 (*)

W14

Table 19

Figure 20

ADS5463 (*)

W14

Table 19

Figure 20

ADS5474 (*)

W14

Table 19

Figure 20

RXA as baseband

Yes

Baseband format

– W14

Table 21

Figure 20

TX input

ADS61xx, ADS41xx,

Yes

Table 20

Figure 20

ADS62pxx

ADS55xx

Yes

B7, W7

Table 20Table 18

Figure 20

ADS58B18

Yes

B7, W7

Table 20Table 18

Figure 20

ADS58B28,

Yes

B7, W7

Table 20Table 18

Figure 20

ADS62c1x

ADS64xx

6 or 7

Yes

Table 18

Figure 21

ADS52xx

12 or 14

Yes

Table 18

Figure 21

Table 18. RX ADC-W7 Switching Characteristics

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

fCLK(ADC)

RX input clock frequency, ADCA7 Clk

See (1)

620

MHz

Input data setup time on port A before ADCA7

tsu(ADC,A)

See (1)(2)

260

Clk transition

Input data hold time on port A after ADCA7 Clk

th(ADC,A)

See (1)(2)

170

transition

Input data setup time on port B before ADCB7

tsu(ADC,B)

See (1)(2)

260

Clk transition

Input data hold time on port B after ADCB7 Clk

th(ADC,B)

See (1)(2)

140

transition

(1)

Chip specifications are production tested at 90

°C case temperature for the given specification. Early production lots are sample tested

–40°C.

(2)

Setup and hold times apply to data and appropriate ADC Clk, respectively. Timing is measured from ADC Clk threshold crossing.

Figure 20. RX ADC LVDS Timing Specifications (RXA and RXB)

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