DAC5682 datasheet(23/49 Pages) TI

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GC5330

GC5337

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SLWS226 B

– DECEMBER 2010 – REVISED JANUARY 2011

The widest-band feedback is seen directly from the ADC interface to the capture buffer. Further RX processing to

get the complex data to the capture buffer requires that the complex rate is one-half the DPD clock rate or lower.

RX Sub-Chips

Each of two RX sub-chips consists of the following blocks (each block may be optionally bypassed), which

operate on a per-stream basis:

•

DC offset cancellation

•

Front-end automatic gain control (feAGC)

•

Real-to-Complex (R2C) conversion

•

Switch for replicating or moving streams across the four paths (per sub-chip)

•

IF NCO for complex mixing (frequency translation)

•

Bulk downconverter (BDC)

•

Equalizer

•

IQ imbalance correction

DC offset cancellation

The dc offset canceller can be programmed to integrate a number of input samples automatically, divide by a

power of 2, and subtract the mean offset or a programmed offset from the input. The input can be real or

complex. Each input ADC has a separate cancellation for each RX block channel.

Front-end AGC

The feAGC block is used to control the RX ADC input level by controlling an external DVGA.

The feAGC has multiple channels in each RX block:

•

1 real stream up to 4

× DPD clock rate (only use one block)

•

2 real (using both blocks) or 1 complex stream (only use one block) up to 2

× DPD clock rate each

•

4 real or 2 complex streams up to DPD clock rate each (uses both blocks)

•

8 real or 4 complex streams up to 1/2 DPD clock rate each (uses both blocks)

The feAGC has both threshold comparison and an integrated power measurement. The feAGC has an error

accumulation. The error accumulation can be mapped to a specific ADC desired operating point. The integral

controller outputs the DVGA value to control the ADC input. DVGA controls are mapped to the specific DVGA

outputs, supporting multiple DVGA types. Multipliers in the data path can be used to compensate for external

DVGA gain changes (from the feAGC output control word). A delay block aligns the gain value applied to the

internal multiplier with the point in time on the data samples where the external gain change was applied. Use of

this multiplier minimizes gain steps that would cause transients in the downstream digital filters and allows

relative power measurements on the digital signals.

The AGC operation may be suspended during certain conditions. The internal controlled-delay AGC update and

special clock gating can be used to suspend the AGC operation.

The control word outputs from the feAGC blocks are applied to external DVGA parts via the DVGA pins. There

are 16 DVGA pins (3.3-V CMOS) which may be individually configured as DVGA output signals or GPIO (input or

output) signals. When used as DVGA control signals, there are two modes:

•

Transparent mode

– parallel output words are connected directly to DVGAs that are being used in a mode

without a clock or latch signal to clock-in the gain word. This is the minimum latency mode. There can be two

ports of 8 bits each, three ports of 5 bits each, four ports of 4 bits each, or five ports of 3 bits each.

•

Clocked mode

– eight latch enable (LE) signals and one 8-bit output word. This mode allows up to eight

control signals, up to 8 bits each, but with increased latency. The LE signal may be a positive or negative

pulse, with programmable width.

R2C

In the real-to-complex conversion block, real signal inputs are up- or downconverted by fS/4, filtered to isolate the

selected sideband, and decimated by a factor of 2. Real-to-complex conversion is bypassed for complex inputs.

The rejection of the R2C decimation filter is:

•

For 90% bandwidth signal,

–68 dB, stop band

•

For 80% bandwidth signal,

–106 dB, stop band

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