Q0-E

Qn-D

Qn-H

Qn-E

In-D

Qn-D

I0-E

Qn-B

Qn-F

In-E

In-B

Qn-B

Q1-E

Q0-D

I0-H

Q0-E

I0-D

I0-D

I1-E

Q0-B

I0-F

I0-E

I0-B

I0-B

Q0-O

Qn-C

Qn-G

Qn-O

In-C

Qn-C

I0-O

Qn-A

Qn-E

In-O

In-A

Qn-A

Q1-O

Q0-C

I0-G

Q0-O

I0-C

I0-C

I1-O

Q0-A

I0-E

I0-O

I0-A

I0-A

‘n’ can be up to 47, ‘O’ is 8 (or 9) odd numbered bits (1, 3, 5, ...), ‘E’ is 8 (or 9) even numbered bits (0, 2, 4, ...), with 0 being the LSB

‘n’ can be up to 47, ‘A’ is 4 MSBs, ‘B’ is next 4 bits, ‘C’ is next 4 bits and ‘D’ is 4 LSBs

BB

Data 0

OUT

BB

Data 0

OUT

BB

Data 0

OUT

BBOUT Clk 0

(if DDR Mode 0)

BB

Clk 0

(if DDR Mode 0)

OUT

BBOUT Clk

0

(if DDR Mode 0)

OUT

BB

Clk 0

(if DDR Mode 1 or 2)

OUT

BB

Clk 0

(if DDR Mode 1 or 2)

OUT

BB

Clk 0

(if DDR Mode 1 or 2)

OUT

BB

Sync 0

OUT

BB

Sync 0

OUT

BB

Sync 0

OUT

T0505-01

Mode 1B

18 bit I/Q Data

9I, 9I, 9Q, 9Q

Mode 1BF

16 bit I/Q Data + 4 bits gain

8I +1G, 8I + 1G, 8Q + 1G, 8Q + 1G

Modes 1N, 2N

16 bit I/Q Data

4I, 4I, 4I, 4I, 4Q, 4Q, 4Q, 4Q

Modes 1NF, 2NF

14 bit I/Q Data + 4 bits gain

4I, 4I, 4I, 2I +2Q, 4Q, 4Q, 4Q, 4G

Modes 1S, 2S, 3S

16 bit I/Q Data

4I, 4I, 4I, 4I, 4Q, 4Q, 4Q, 4Q

Modes 1SF, 2SF, 3SF

14 bit I/Q Data + 4 bits gain

4I, 4I, 4I, 2I +2Q, 4Q, 4Q, 4Q, 4G

‘n’ can be up to 47, ‘A’ is 2 MSBs, ‘B’ is next 2 bits, ‘C’ is next 2 bits, ... and ‘H’ is 2 LSBs

Qn-D

Qn-H

Qn-H

In-D

Qn-D

Qn-D

Qn-B

Qn-F

Qn-F

In-B

Qn-B

Qn-B

Q0-D

I0-H

I0-H

I0-D

I0-D

I0-D

Q0-B

I0-F

I0-F

I0-B

I0-B

I0-B

Qn-C

Qn-G

Qn-G

In-C

Qn-C

Qn-C

Qn-A

Qn-E

Qn-E

In-A

Qn-A

Qn-A

Q0-C

I0-G

I0-G

I0-C

I0-C

I0-C

Q0-A

I0-E

I0-E

I0-A

I0-A

I0-A

BB

Data 1

OUT

BB

Data 1

OUT

BB

Data 2

OUT

BBOUT Clk 1

(if DDR Mode 0)

BB

Clk 1

(if DDR Mode 0)

OUT

BBOUT Clk 2

(if DDR Mode 0)

BB

Clk 1

(if DDR Mode 1 or 2)

OUT

BB

Clk 1

(if DDR Mode 1 or 2)

OUT

BB

Clk 2

(if DDR Mode 1 or 2)

OUT

BB

Sync 1

OUT

BB

Sync 1

OUT

BB

Sync 2

OUT

GC5330

GC5337

SLWS226 B

– DECEMBER 2010 – REVISED JANUARY 2011

www.ti.com

Table 8. RX BB Pin Assignments

LVDS Pair BBI[11:0]

Byte Mode

Nibble Mode

Serial Mode

BBOUT[0] pos. and neg.

BB0_DATA_0

BB0_DATA_0

BB0_DATA_0

BBOUT[1] pos. and neg.

BB0_DATA_1

BB0_DATA_1

BB0_DATA_1

BBOUT[2] pos. and neg.

BB0_DATA_2

BB0_SYNC

BB0_SYNC

BBOUT[3] pos. and neg.

Spare

BB0_CLOCK

BB0_CLOCK

BBOUT[4] pos. and neg.

BB0_DATA_3

BB0_DATA_2

BB1_DATA_0

BBOUT[5] pos. and neg.

BB0_DATA_4

BB0_DATA_3

BB1_DATA_1

BBOUT[6] pos. and neg.

BB0_SYNC

BB1_SYNC

BB1_SYNC

BBOUT[7] pos. and neg.

BB0_CLOCK

BB1_CLOCK

BB1_CLOCK

BBOUT[8] pos. and neg.

BB0_DATA_5

BB1_DATA_0

BB2_DATA_0

BBOUT[9] pos. and neg.

BB0_DATA_6

BB1_DATA_1

BB2_DATA_1

BBOUT[10] pos. and neg.

BB0_DATA_7

BB1_DATA_2

BB2_SYNC

BBOUT[11] pos. and neg.

BB0_DATA_8

BB1_DATA_3

BB2_CLOCK

Number of BBdata streams

1

2

3

Number of DDR clocks to transfer 1 complex sample

2

4

8

Figure 13. RX BB Formats

26

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