DAC5682 datasheet(14/49 Pages) TI

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GC5330

GC5337

SLWS226 B

– DECEMBER 2010 – REVISED JANUARY 2011

www.ti.com

Table 2. TX BB Formatter Modes

Maximum Complex Interface Rate per Channel

MODE

DESCRIPTION

Total Number of Interface Pins

N is the number of channels.

Byte mode, 1 interface rate

10 or 11 = 8 or 9 data + 1 clk + 1

(Clk

× 4/4)/N; maximum 192.31 MSPS total (for all

sync

channels)

Nibble mode, 1 interface rate

6 = 4 data + 1 clk + 1 sync

(Clk

× 4/8)/N; maximum 125 (Nibble 0), 96.15 (Nibble

1) MSPS total

Serial mode, 1 interface rate

4 = 2 data + 1 clk + 1 sync

(Clk

× 4/16)/N; maximum 48.07 MSPS total

Nibble mode, 2 interface rates

12 = 4 data + 1 clk + 1 sync + 4

(Clk

× 4/8)/N × 2; maximum 221.15 MSPS total

data + 1 clk + 1 sync

’(1)

Nibble + byte mode, 2 interface

16 = 4 data + 1 clk + 1 sync + 8

Nibble port: (Clk

× 4/8)/N; maximum 125 MSPS total

rates,

data + 1 clk + 1 sync

Byte port: (Clk

× 2/4)/N; maximum 125, 250 MSPS

RX-ADC input pins used for

total

byte-mode port.

Serial mode, 2 interface rates

8 = 2 data + 1 clk + 1 sync + 2 data

(Clk

× 4/16)/N; maximum 96.15 MSPS total

+ 1 clk + 1 sync

Serial mode, 3 interface rates

12 = 2 data + 1 clk+1 sync + 2 data

(Clk

× 4/16)/N; maximum 144.23 MSPS total

+ 1 clk + 1 sync + 2 data + 1 clk + 1

sync

(1)

’ is the only configuration that allows a special mode to re-use RX input port A as baseband TX inputs

Table 3. TX BB Pin Assignments

LVDS PAIR BBI[11:0]

BYTE MODE

NIBBLE MODE

SERIAL MODE

BBIN[0] pos. and neg.

BB0_DATA_0

BBIN[1] pos. and neg.

BB0_DATA_1

BBIN[2] pos. and neg.

BB0_DATA_2

BB0_SYNC

BBIN[3] pos. and neg.

Spare

BB0_CLOCK

BBIN[4] pos. and neg.

BB0_DATA_3

BB0_DATA_2

BB1_DATA_0

BBIN[5] pos. and neg.

BB0_DATA_4

BB0_DATA_3

BB1_DATA_1

BBIN[6] pos. and neg.

BB0_SYNC

BB1_SYNC

BBIN[7] pos. and neg.

BB0_CLOCK

BB1_CLOCK

BBIN[8] pos. and neg.

BB0_DATA_5

BB1_DATA_0

BB2_DATA_0

BBIN[9] pos. and neg.

BB0_DATA_6

BB1_DATA_1

BB2_DATA_1

BBIN[10] pos. and neg.

BB0_DATA_7

BB1_DATA_2

BB2_SYNC

BBIN[11] pos. and neg.

BB0_DATA_8

BB1_DATA_3

BB2_CLOCK

Number of BBdata streams

Number of DDR clocks to transfer 1 complex sample

The actual data transfer rate in nibble mode is 2 times higher than the byte mode for the same total throughput. If

two ports are required (e.g., to support two different sample rates), and a lower speed on the interface is desired,

the GC533x can re-use the RX ADC input port A as a baseband TX input bus. RX ADC port A has 15 pairs of

LVDS input pins and supports one set of baseband input data in byte mode. When RX port A is used as a

baseband TX input, it cannot be also used as an RX input port.

The baseband interface supports a full-clock or gated-clock format. These formats are shown in Figure 11

The mapping for the RX port A pins when in BB TX input mode is:

•

RXA14: clock

•

RXA13: sync

•

RXA12

–5: BB0_DATA7–0

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