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ST72F262G2B5 Datasheet(PDF) 90 Page - STMicroelectronics |
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ST72F262G2B5 Datasheet(HTML) 90 Page - STMicroelectronics |
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90 / 172 page  ST72260Gx, ST72262Gx, ST72264Gx 90/172 SERIAL COMMUNICATIONS INTERFACE (Cont’d) 11.5.4.2 Transmitter The transmitter can send data words of either 8 or 9 bits depending on the M bit status. When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the T8 bit in the SCICR1 register. Character Transmission During an SCI transmission, data shifts out least significant bit first on the TDO pin. In this mode, the SCIDR register consists of a buffer (TDR) be- tween the internal bus and the transmit shift regis- ter (see Figure 53). Procedure – Select the M bit to define the word length. – Select the desired baud rate using the SCIBRR and the SCIETPR registers. – Set the TE bit to assign the TDO pin to the alter- nate function and to send a idle frame as first transmission. – Access the SCISR register and write the data to send in the SCIDR register (this sequence clears the TDRE bit). Repeat this sequence for each data to be transmitted. Clearing the TDRE bit is always performed by the following software sequence: 1. An access to the SCISR register 2. A write to the SCIDR register The TDRE bit is set by hardware and it indicates: – The TDR register is empty. – The data transfer is beginning. – The next data can be written in the SCIDR regis- ter without overwriting the previous data. This flag generates an interrupt if the TIE bit is set and the I bit is cleared in the CCR register. When a transmission is taking place, a write in- struction to the SCIDR register stores the data in the TDR register and which is copied in the shift register at the end of the current transmission. When no transmission is taking place, a write in- struction to the SCIDR register places the data di- rectly in the shift register, the data transmission starts, and the TDRE bit is immediately set. When a frame transmission is complete (after the stop bit or after the break frame) the TC bit is set and an interrupt is generated if the TCIE is set and the I bit is cleared in the CCR register. Clearing the TC bit is performed by the following software sequence: 1. An access to the SCISR register 2. A write to the SCIDR register Note: The TDRE and TC bits are cleared by the same software sequence. Break Characters Setting the SBK bit loads the shift register with a break character. The break frame length depends on the M bit (see Figure 54). As long as the SBK bit is set, the SCI send break frames to the TDO pin. After clearing this bit by software the SCI insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame. Idle Characters Setting the TE bit drives the SCI to send an idle frame before the first data frame. Clearing and then setting the TE bit during a trans- mission sends an idle frame after the current word. Note: Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the best time to toggle the TE bit is when the TDRE bit is set i.e. before writing the next byte in the SCIDR. |
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