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ST72F262G2B5 Datasheet(PDF) 22 Page - STMicroelectronics |
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ST72F262G2B5 Datasheet(HTML) 22 Page - STMicroelectronics |
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22 / 172 page  ST72260Gx, ST72262Gx, ST72264Gx 22/172 6.3 RESET SEQUENCE MANAGER (RSM) 6.3.1 Introduction The reset sequence manager includes three RE- SET sources as shown in Figure 12: ■ External RESET source pulse ■ Internal LVD RESET (Low Voltage Detection) ■ Internal WATCHDOG RESET These sources act on the RESET pin and it is al- ways kept low during the delay phase. The RESET service routine vector is fixed at ad- dresses FFFEh-FFFFh in the ST7 memory map. The basic RESET sequence consists of 3 phases as shown in Figure 11: ■ Active Phase depending on the RESET source ■ 4096 CPU clock cycle delay (selected by option byte) ■ RESET vector fetch The 4096 CPU clock cycle delay allows the oscil- lator to stabilise and ensures that recovery has taken place from the Reset state. The shorter or longer clock cycle delay should be selected by op- tion byte to correspond to the stabilization time of the external oscillator used in the application. The RESET vector fetch phase duration is 2 clock cycles. Figure 11. RESET Sequence Phases 6.3.2 Asynchronous External RESET pin The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in ac- cordance with the input voltage. It can be pulled low by external circuitry to reset the device. See Electrical Characteristic section for more details. A RESET signal originating from an external source must have a duration of at least th(RSTL)in in order to be recognized (see Figure 13). This de- tection is asynchronous and therefore the MCU can enter reset state even in HALT mode. Figure 12. Reset Block Diagram RESET Active Phase INTERNAL RESET 4096 CLOCK CYCLES FETCH VECTOR RESET RON VDD WATCHDOG RESET LVD RESET INTERNAL RESET PULSE GENERATOR Filter |
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