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ST72F262G2B5 Datasheet(PDF) 31 Page - STMicroelectronics |
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ST72F262G2B5 Datasheet(HTML) 31 Page - STMicroelectronics |
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31 / 172 page  ST72260Gx, ST72262Gx, ST72264Gx 31/172 INTERRUPTS (Cont’d) 7.5 INTERRUPT REGISTER DESCRIPTION CPU CC REGISTER INTERRUPT BITS Read/Write Reset Value: 111x 1010 (xAh) Bit 5, 3 = I1, I0 Software Interrupt Priority These two bits indicate the current interrupt soft- ware priority. These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software pri- ority registers (ISPRx). They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and PUSH/POP in- structions (see “Interrupt Dedicated Instruction Set” table). *Note: TRAP and RESET events are non maska- ble sources and can interrupt a level 3 program. INTERRUPT SOFTWARE PRIORITY REGIS- TERS (ISPRX) Read/Write (bits 7:4 of ISPR3 are read only) Reset Value: 1111 1111 (FFh) These four registers contain the interrupt software priority of each interrupt vector. – Each interrupt vector (except RESET and TRAP) has corresponding bits in these registers where its own software priority is stored. This corre- spondance is shown in the following table. – Each I1_x and I0_x bit value in the ISPRx regis- ters has the same meaning as the I1 and I0 bits in the CC register. – Level 0 can not be written (I1_x=1, I0_x=0). In this case, the previously stored value is kept. (ex- ample: previous=CFh, write=64h, result=44h) The RESET and TRAP vectors have no software priorities. When one is serviced, the I1 and I0 bits of the CC register are both set. Caution: If the I1_x and I0_x bits are modified while the interrupt x is executed the following be- haviour has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previ- ous one, the interrupt x is re-entered. Otherwise, the software priority stays unchanged up to the next interrupt request (after the IRET of the inter- rupt x). 70 11 I1 H I0 NZC Interrupt Software Priority Level I1 I0 Level 0 (main) Low High 10 Level 1 0 1 Level 2 0 0 Level 3 (= interrupt disable*) 1 1 70 ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0 ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4 ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8 ISPR3 1 1 1 1 I1_13 I0_13 I1_12 I0_12 Vector Address ISPRx Bits FFFBh-FFFAh ei0 FFF9h-FFF8h ei1 ... ... FFE1h-FFE0h Not used |
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