 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ST72F262G2B5 Datasheet(PDF) 18 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
ST72F262G2B5 Datasheet(HTML) 18 Page - STMicroelectronics |
|
|
18 / 172 page  ST72260Gx, ST72262Gx, ST72264Gx 18/172 CENTRAL PROCESSING UNIT (Cont’d) Condition Code Register (CC) Read/Write Reset Value: 111x1xxx The 8-bit Condition Code register contains the in- terrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP in- structions. These bits can be individually tested and/or con- trolled by specific instructions. Arithmetic Management Bits Bit 4 = H Half carry. This bit is set by hardware when a carry occurs be- tween bits 3 and 4 of the ALU during an ADD or ADC instructions. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruc- tion. The H bit is useful in BCD arithmetic subrou- tines. Bit 2 = N Negative. This bit is set and cleared by hardware. It is repre- sentative of the result sign of the last arithmetic, logical or data manipulation. It’s a copy of the re- sult 7th bit. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (i.e. the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instruc- tions. Bit 1 = Z Zero. This bit is set and cleared by hardware. This bit in- dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. Bit 0 = C Carry/borrow. This bit is set and cleared by hardware and soft- ware. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions. Interrupt Management Bits Bit 5,3 = I1, I0 Interrupt The combination of the I1 and I0 bits gives the cur- rent interrupt software priority. These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software pri- ority registers (IxSPR). They can be also set/ cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions. See the interrupt management chapter for more details. 70 11 I1 H I0 N Z C Interrupt Software Priority I1 I0 Level 0 (main) 1 0 Level 1 0 1 Level 2 0 0 Level 3 (= interrupt disable) 1 1 |
Similar Part No. - ST72F262G2B5 |
|
Similar Description - ST72F262G2B5 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
