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ST72F262G2B5 Datasheet(PDF) 25 Page - STMicroelectronics

Part # ST72F262G2B5
Description  8-BIT MCU WITH FLASH OR ROM MEMORY, ADC, TWO 16-BIT TIMERS, I2C, SPI, SCI INTERFACES
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72F262G2B5 Datasheet(HTML) 25 Page - STMicroelectronics

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SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.2 Auxiliary Voltage Detector (AVD)
The Voltage Detector function (AVD) is based on
an analog comparison between a VIT- and VIT+ ref-
erence value and the VDD main supply. The VIT-
reference value for falling voltage is lower than the
VIT+ reference value for rising voltage in order to
avoid parasitic detection (hysteresis).
The output of the AVD comparator is directly read-
able by the application software through a real
time status bit (VDF) in the SICSR register. This bit
is read only.
Caution: The AVD functions only if the LVD is en-
abled through the option byte.
6.4.2.1 Monitoring the VDD Main Supply
The AVD voltage threshold value is relative to the
selected LVD threshold configured by option byte
(see Section 15.1 on page 162).
If the AVD interrupt is enabled, an interrupt is gen-
erated when the voltage crosses the VIT+(AVD) or
VIT-(AVD) threshold (AVDF bit toggles).
In the case of a drop in voltage, the AVD interrupt
acts as an early warning, allowing software to shut
down safely before the LVD resets the microcon-
troller. See Figure 15.
The interrupt on the rising edge is used to inform
the application that the VDD warning state is over.
If the voltage rise time trv is less than 256 or 4096
CPU cycles (depending on the reset delay select-
ed by option byte), no AVD interrupt will be gener-
ated when VIT+(AVD) is reached.
If trv is greater than 256 or 4096 cycles then:
– If the AVD interrupt is enabled before the
VIT+(AVD) threshold is reached, then 2 AVD inter-
rupts will be received: the first when the AVDIE
bit is set, and the second when the threshold is
reached.
– If the AVD interrupt is enabled after the VIT+(AVD)
threshold is reached then only one AVD interrupt
will occur.
Figure 15. Using the AVD to Monitor VDD
VDD
VIT+(AVD)
VIT-(AVD)
AVDF bit
0
0
RESET VALUE
IF AVDIE bit = 1
Vhyst
AVD INTERRUPT
REQUEST
INTERRUPT PROCESS
INTERRUPT PROCESS
VIT+(LVD)
VIT-(LVD)
LVD RESET
Early Warning Interrupt
(Power has dropped, MCU not
not yet in reset)
1
1
trv VOLTAGE RISE TIME


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