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EP3SL70 Datasheet(PDF) 108 Page - Altera Corporation |
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EP3SL70 Datasheet(HTML) 108 Page - Altera Corporation |
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108 / 341 page  1–98 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Stratix III Device Handbook, Volume 2 © July 2010 Altera Corporation Table 1–63 lists the EP3SL110 column pins output timing parameters for single-ended I/O standards. 1.2-V HSTL CLASS I GCLK t su -0.754 -0.795 -1.135 -1.224 -1.312 -1.266 -1.596 -1.226 -1.310 -1.267 -1.639 ns t h 0.871 0.928 1.324 1.432 1.542 1.485 1.815 1.443 1.550 1.496 1.858 ns GCLK PLL t su 1.087 1.100 1.765 1.995 2.226 2.111 2.053 2.008 2.242 2.125 2.100 ns t h -0.835 -0.832 -1.364 -1.547 -1.727 -1.640 -1.575 -1.551 -1.733 -1.644 -1.619 ns 1.2-V HSTL CLASS II GCLK t su -0.754 -0.795 -1.135 -1.224 -1.312 -1.266 -1.596 -1.226 -1.310 -1.267 -1.639 ns t h 0.871 0.928 1.324 1.432 1.542 1.485 1.815 1.443 1.550 1.496 1.858 ns GCLK PLL t su 1.087 1.100 1.765 1.995 2.226 2.111 2.053 2.008 2.242 2.125 2.100 ns t h -0.835 -0.832 -1.364 -1.547 -1.727 -1.640 -1.575 -1.551 -1.733 -1.644 -1.619 ns 3.0-V PCI GCLK t su -0.916 -0.894 -1.249 -1.442 -1.562 -1.607 -1.846 -1.464 -1.556 -1.610 -1.886 ns t h 1.031 1.026 1.437 1.649 1.795 1.825 2.069 1.681 1.799 1.836 2.109 ns GCLK PLL t su 0.986 1.002 1.649 1.861 1.973 1.857 1.801 1.871 1.993 1.875 1.851 ns t h -0.735 -0.735 -1.249 -1.411 -1.472 -1.385 -1.319 -1.412 -1.481 -1.393 -1.366 ns 3.0-V PCI-X GCLK t su -0.916 -0.894 -1.249 -1.442 -1.562 -1.607 -1.846 -1.464 -1.556 -1.610 -1.886 ns t h 1.031 1.026 1.437 1.649 1.795 1.825 2.069 1.681 1.799 1.836 2.109 ns GCLK PLL t su 0.986 1.002 1.649 1.861 1.973 1.857 1.801 1.871 1.993 1.875 1.851 ns t h -0.735 -0.735 -1.249 -1.411 -1.472 -1.385 -1.319 -1.412 -1.481 -1.393 -1.366 ns Table 1–62. EP3SL110 Row Pins Input Timing Parameters (Part 3 of 3) I/O Standard Clock Fast Model C2 C3 C4 C4L I3 I4 I4L Units Industrial Commercial V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V Table 1–63. EP3SL110 Column Pins Output Timing Parameters (Part 1 of 7) I/O Standard Clock Fast Model C2 C3 C4 C4L I3 I4 I4L Units Industrial Commercial V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V 3.3-V LVTTL 4mA GCLK tco 3.439 3.439 4.768 5.145 5.638 5.507 5.801 5.145 5.638 5.507 5.801 ns GCLK PLL t co 3.829 3.829 5.344 5.778 6.326 6.168 6.550 5.778 6.326 6.168 6.550 ns 8mA GCLK tco 3.372 3.372 4.659 5.034 5.525 5.394 5.688 5.034 5.525 5.394 5.688 ns GCLK PLL t co 3.762 3.762 5.235 5.667 6.213 6.055 6.437 5.667 6.213 6.055 6.437 ns 12mA GCLK t co 3.286 3.286 4.556 4.936 5.433 5.302 5.596 4.936 5.433 5.302 5.596 ns GCLK PLL t co 3.676 3.676 5.131 5.568 6.121 5.963 6.345 5.568 6.121 5.963 6.345 ns 16mA GCLK t co 3.279 3.279 4.539 4.908 5.392 5.261 5.555 4.908 5.392 5.261 5.555 ns GCLK PLL t co 3.669 3.669 5.114 5.540 6.080 5.922 6.304 5.540 6.080 5.922 6.304 ns |
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