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EP3SL340 Datasheet(PDF) 129 Page - Altera Corporation

Part # EP3SL340
Description  Stratix III Device Handbook
PDF  341 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP3SL340 Datasheet(HTML) 129 Page - Altera Corporation

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Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
1–119
I/O Timing
© July 2010
Altera Corporation
Stratix III Device Handbook, Volume 2
Table 1–70 lists the EP3SL110 row pin delay adders when using the regional clock.
EP3SL150 I/O Timing Parameters
Table 1–71 through Table 1–74 list the maximum I/O timing parameters for EP3SL150
devices for single-ended I/O standards.
Table 1–71 lists the EP3SL150 column pins input timing parameters for single-ended
I/O standards.
Table 1–70. EP3SL110 Row Pin Delay Adders for Regional Clock
Parameter
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Industrial
Commercial
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
RCLK input adder
0.086
0.109
0.158
0.16
0.161
0.159
0.281
0.137
0.153
0.153
0.285
ns
RCLK PLL input adder
0.075
0.075
0.117
0.123
0.129
0.125
0.222
0.113
0.118
0.114
0.226
ns
RCLK output adder
-0.072
-0.097
-0.137
-0.135
-0.116
-0.134
-0.24
-0.11
-0.104
-0.124
-0.244
ns
RCLK PLL output adder
-0.063
-0.065
-0.097
-0.1
-0.104
-0.101
-0.198
-0.088
-0.09
-0.088
-0.201
ns
Table 1–71. EP3SL150 Column Pins Input Timing Parameters (Part 1 of 3)
I/O
Standard
Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Industrial
Commercial
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
3.3-V LVTTL
GCLK
t
su
-0.986
-0.964
-1.402 -1.558 -1.797 -1.778 -2.106 -1.558 -1.797 -1.778 -2.106
ns
t
h
1.119
1.093
1.584
1.767
2.027
1.996
2.327
1.767
2.027
1.996
2.327
ns
GCLK
PLL
t
su
-1.278
-1.221
-1.771 -1.984 -2.197 -2.123 -2.542 -1.984 -2.197 -2.123 -2.542
ns
t
h
1.556
1.499
2.175
2.439
2.697
2.598
3.034
2.439
2.697
2.598
3.034
ns
3.3-V
LVCMOS
GCLK
t
su
-0.986
-0.964
-1.402 -1.558 -1.797 -1.778 -2.106 -1.558 -1.797 -1.778 -2.106
ns
t
h
1.119
1.093
1.584
1.767
2.027
1.996
2.327
1.767
2.027
1.996
2.327
ns
GCLK
PLL
t
su
-1.278
-1.221
-1.771 -1.984 -2.197 -2.123 -2.542 -1.984 -2.197 -2.123 -2.542
ns
t
h
1.556
1.499
2.175
2.439
2.697
2.598
3.034
2.439
2.697
2.598
3.034
ns
3.0-V LVTTL
GCLK
t
su
-0.997
-0.975
-1.401 -1.560 -1.796 -1.777 -2.105 -1.560 -1.796 -1.777 -2.105
ns
t
h
1.130
1.104
1.583
1.769
2.026
1.995
2.326
1.769
2.026
1.995
2.326
ns
GCLK
PLL
t
su
-1.289
-1.232
-1.770 -1.986 -2.196 -2.122 -2.541 -1.986 -2.196 -2.122 -2.541
ns
t
h
1.567
1.510
2.174
2.441
2.696
2.597
3.033
2.441
2.696
2.597
3.033
ns
3.0-V
LVCMOS
GCLK
t
su
-0.997
-0.975
-1.401 -1.560 -1.796 -1.777 -2.105 -1.560 -1.796 -1.777 -2.105
ns
t
h
1.130
1.104
1.583
1.769
2.026
1.995
2.326
1.769
2.026
1.995
2.326
ns
GCLK
PLL
t
su
-1.289
-1.232
-1.770 -1.986 -2.196 -2.122 -2.541 -1.986 -2.196 -2.122 -2.541
ns
t
h
1.567
1.510
2.174
2.441
2.696
2.597
3.033
2.441
2.696
2.597
3.033
ns
2.5 V
GCLK
t
su
-0.992
-0.970
-1.410 -1.572 -1.815 -1.796 -2.124 -1.572 -1.815 -1.796 -2.124
ns
t
h
1.125
1.099
1.592
1.781
2.045
2.014
2.345
1.781
2.045
2.014
2.345
ns
GCLK
PLL
t
su
-1.284
-1.227
-1.779 -1.998 -2.215 -2.141 -2.560 -1.998 -2.215 -2.141 -2.560
ns
t
h
1.562
1.505
2.183
2.453
2.715
2.616
3.052
2.453
2.715
2.616
3.052
ns



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