EP2C8A datasheet(159/168 Pages) ALTERA

159 / 168 page

Altera Corporation

5–69

February 2008

Cyclone II Device Handbook, Volume 1

DC Characteristics and Timing Specifications

Figure 5–10. DCD Measurement Technique for DDIO (Double-Data Rate) Outputs

When an FPGA PLL generates the internal clock, the PLL output clocks

the IOE block. As the PLL only monitors the positive edge of the reference

clock input and internally re-creates the output clock signal, any DCD

present on the reference clock is filtered out. Therefore, the DCD for a

DDIO output with PLL in the clock path is better than the DCD for a

DDIO output without PLL in the clock path.

Tables 5–55 through 5–58 give the maximum DCD in absolution

derivation for different I/O standards on Cyclone II devices. Examples

are also provided that show how to calculate DCD as a percentage.

PRN

CLRN

DFF

INPUT

VCC

clk

output

PRN

CLRN

DFF

VCC

GND

Table 5–55. Maximum DCD for Single Data Outputs (SDR) on Row I/O

Pins Notes (1), (2) (Part 1 of 2)

Row I/O Output Standard

Unit

LVCMOS

165

230

LVTTL

195

255

2.5-V

120

135

1.8-V

115

175

1.5-V

130

135

SSTL-2 Class I

SSTL-2 Class II

SSTL-18 Class I

165

HSTL-15 Class I

145

205

HSTL-18 Class I

155

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