EP2C8A datasheet(155/168 Pages) ALTERA

155 / 168 page

Altera Corporation

5–65

February 2008

Cyclone II Device Handbook, Volume 1

DC Characteristics and Timing Specifications

Table 5–53 shows the JTAG timing parameters and values for Cyclone II

devices.

Cyclone II devices must be within the first 17 devices in a JTAG

chain. All of these devices have the same JTAG controller. If any

of the Cyclone II devices are in the 18th position or after they will

fail configuration. This does not affect the SignalTap® II logic

analyzer.

For more information on JTAG, refer to the IEEE 1149.1 (JTAG)

Boundary-Scan Testing for Cyclone II Devices chapter in the Cyclone II

Handbook.

Table 5–53. Cyclone II JTAG Timing Parameters and Values

Symbol

Parameter

Min

Max

Unit

tJCP

TCK clock period

—

tJCH

TCK clock high time

—

tJCL

TCK clock low time

—

tJPSU

JTAG port setup time (2)

5—

tJPH

JTAG port hold time

—

tJPCO

JTAG port clock to output (2)

—13

tJPZX

JTAG port high impedance to valid output (2)

—13

tJPXZ

JTAG port valid output to high impedance (2)

—13

tJSSU

Capture register setup time (2)

5—

tJSH

Capture register hold time

—

tJSCO

Update register clock to output

—

tJSZX

Update register high impedance to valid output

—

tJSXZ

Update register valid output to high impedance

—

Notes to Table 5–53:

(1)

This information is preliminary.

(2)

This specification is shown for 3.3-V LVTTL/LVCMOS and 2.5-V LVTTL/LVCMOS operation of the JTAG pins. For

1.8-V LVTTL/LVCMOS and 1.5-V LVCMOS, the JTAG port and capture register clock setup time is 3 ns and port

clock to output time is 15 ns.

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