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EP2C8A Datasheet(PDF) 153 Page - Altera Corporation |
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EP2C8A Datasheet(HTML) 153 Page - Altera Corporation |
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153 / 168 page  Altera Corporation 5–63 February 2008 Cyclone II Device Handbook, Volume 1 DC Characteristics and Timing Specifications External Memory Interface Specifications Table 5–52 shows the DQS bus clock skew adder specifications. Table 5–51. LVDS Receiver Timing Specification Symbol Conditions –6 Speed Grade –7 Speed Grade –8 Speed Grade Unit Min Typ Max Min Typ Max Min Typ Max fHSCLK (input clock frequency) ×10 10 — 402.5 10 — 320 10 — 320 (1) MHz ×8 10 — 402.5 10 — 320 10 — 320 (1) MHz ×7 10 — 402.5 10 — 320 10 — 320 (1) MHz ×4 10 — 402.5 10 — 320 10 — 320 (1) MHz ×2 10 — 402.5 10 — 320 10 — 320 (1) MHz ×1 10 — 402.5 10 — 402.5 10 — 402.5 (3) MHz HSIODR ×10 100 — 805 100 — 640 100 — 640 (2) Mbps ×8 80 — 805 80 — 640 80 — 640 (2) Mbps ×7 70 — 805 70 — 640 70 — 640 (2) Mbps ×4 40 — 805 40 — 640 40 — 640 (2) Mbps ×2 20 — 805 20 — 640 20 — 640 (2) Mbps ×1 10 — 402.5 10 — 402.5 10 — 402.5 (4) Mbps SW — — — 300 — — 400 — — 400 ps Input jitter tolerance — — — 500 — — 500 — — 550 ps tLOCK — — — 100 — — 100 — — 100 (5) ps Notes to Table 5–51: (1) For extended temperature devices, the maximum input clock frequency for x10 through x2 modes is 275 MHz. (2) For extended temperature devices, the maximum data rate for x10 through x2 modes is 550 Mbps. (3) For extended temperature devices, the maximum input clock frequency for x1 mode is 340 MHz. (4) For extended temperature devices, the maximum data rate for x1 mode is 340 Mbps. (5) For extended temperature devices, the maximum lock time is 500 us. Table 5–52. DQS Bus Clock Skew Adder Specifications Mode DQS Clock Skew Adder Unit ×9 155 ps ×18 190 ps Note to Table 5–52: (1) This skew specification is the absolute maximum and minimum skew. For example, skew on a ×9 DQ group is 155 ps or ±77.5 ps. |
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