EP2C8A datasheet(149/168 Pages) ALTERA

149 / 168 page

Altera Corporation

5–59

February 2008

Cyclone II Device Handbook, Volume 1

DC Characteristics and Timing Specifications

Figure 5–5. RSDS Transmitter Clock to Data Relationship

Table 5–49 shows the mini-LVDS transmitter timing budget for Cyclone II

devices at 311 Mbps. Cyclone II devices cannot receive mini-LVDS data

because the devices are intended for applications where they will be

driving display drivers. A maximum mini-LVDS data rate of 311 Mbps is

supported for Cyclone II devices using DDIO registers. Cyclone II

devices support mini-LVDS only in the commercial temperature range.

Transmitter

Valid

Data

Transmitter

Valid

Data

Valid

Data

Total

Skew

Valid

Data

tSU (2 ns)

tH (2 ns)

Channel-to-Channel

Skew (1.68 ns)

Transmitter

Clock (5.88 ns)

At transmitter

tx_data[11..0]

At receiver

rx_data[11..0]

Table 5–49. Mini-LVDS Transmitter Timing Specification (Part 1 of 2)

Symbol

Conditions

–6 Speed Grade

–7 Speed Grade

–8 Speed Grade

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

fHSCLK

(input

clock

frequency)

×10

—

155.5

—

155.5

—

155.5

MHz

×8

—

155.5

—

155.5

—

155.5

MHz

×7

—

155.5

—

155.5

—

155.5

MHz

×4

—

155.5

—

155.5

—

155.5

MHz

×2

—

155.5

—

155.5

—

155.5

MHz

×1

—

311

—

311

—

311

MHz

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