EP2C8A datasheet(147/168 Pages) ALTERA

147 / 168 page

Altera Corporation

5–57

February 2008

Cyclone II Device Handbook, Volume 1

DC Characteristics and Timing Specifications

Figure 5–4. High-Speed I/O Timing Budget

Note (1)

Note to Figure 5–4:

(1)

The equation for the high-speed I/O timing budget is:

period = TCCS + RSKM + SW + RSKM.

Table 5–48 shows the RSDS timing budget for Cyclone II devices at

311 Mbps. RSDS is supported for transmitting from Cyclone II devices.

Cyclone II devices cannot receive RSDS data because the devices are

intended for applications where they will be driving display drivers.

Cyclone II devices support a maximum RSDS data rate of 311 Mbps using

DDIO registers. Cyclone II devices support RSDS only in the commercial

temperature range.

Internal Clock Period

RSKM

0.5

× TCCS

RSKM

0.5

× TCCS

Table 5–48. RSDS Transmitter Timing Specification (Part 1 of 2)

Symbol

Conditions

–6 Speed Grade

–7 Speed Grade

–8 Speed Grade

Unit

Min

Typ

Max(1)

Min

Typ

Max(1)

Min

Typ

Max(1)

fHSCLK

(input

clock

frequency)

×10

—

155.5

—

155.5

—

155.5

MHz

×8

—

155.5

—

155.5

—

155.5

MHz

×7

—

155.5

—

155.5

—

155.5

MHz

×4

—

155.5

—

155.5

—

155.5

MHz

×2

—

155.5

—

155.5

—

155.5

MHz

×1

—

311

—

311

—

311

MHz

Device

operation

in Mbps

×10

100

—

311

100

—

311

100

—

311

Mbps

×8

—

311

—

311

—

311

Mbps

×7

—

311

—

311

—

311

Mbps

×4

—

311

—

311

—

311

Mbps

×2

—

311

—

311

—

311

Mbps

×1

—

311

—

311

—

311

Mbps

tDUTY

—

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