EP2C8A datasheet(151/168 Pages) ALTERA

151 / 168 page

Altera Corporation

5–61

February 2008

Cyclone II Device Handbook, Volume 1

DC Characteristics and Timing Specifications

Tables 5–50 and 5–51 show the LVDS timing budget for Cyclone II

devices. Cyclone II devices support LVDS receivers at data rates up to

805 Mbps, and LVDS transmitters at data rates up to 640 Mbps.

Table 5–50. LVDS Transmitter Timing Specification (Part 1 of 2)

Symbol

Conditions

–6 Speed Grade

–7 Speed Grade

–8 Speed Grade

Unit

Min

Typ

Max

(1)

Max

(2)

Min

Typ

Max

(1)

Max

(2)

Min

Typ

Max

(1)

Max

(2)

fHSCLK

(input

clock

fre-

quency)

×10

—

320

—

275

320

—

155.5

(4)

320

(6)

MHz

×8

—

320

—

275

320

—

155.5

(4)

320

(6)

MHz

×7

—

320

—

275

320

—

155.5

(4)

320

(6)

MHz

×4

—

320

—

275

320

—

155.5

(4)

320

(6)

MHz

×2

—

320

—

275

320

—

155.5

(4)

320

(6)

MHz

×1

—

402.5

—

402.5

—

402.5

(8)

402.5

(8)

MHz

HSIODR

×10

100

—

640

100

—

550

640

100

—

311

(5)

550

(7)

Mbps

×8

—

640

—

550

640

—

311

(5)

550

(7)

Mbps

×7

—

640

—

550

640

—

311

(5)

550

(7)

Mbps

×4

—

640

—

550

640

—

311

(5)

550

(7)

Mbps

×2

—

640

—

550

640

—

311

(5)

550

(7)

Mbps

×1

—

402.5

—

402.5

—

402.5

(9)

402.5

(9)

Mbps

tDUTY

—

———

160

———

312.5

———

363.6

TCCS

(3)

——

—

200

——

200

——

200

Output

jitter

(peak to

peak)

——

—

500

——

500

——

550 (10)

tRISE

20–80%

150

200

250

150

200

250

150

200

250 (11)

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