EP2C8A datasheet(162/168 Pages) ALTERA

162 / 168 page

5–72

Altera Corporation

Cyclone II Device Handbook, Volume 1

February 2008

Duty Cycle Distortion

For DDIO outputs, you can calculate actual half period from the

following equation:

Actual half period = ideal half period – maximum DCD

For example, if the DDR output I/O standard is SSTL-2 Class II, the

maximum DCD for a –5 device is 155 ps (refer to Table 5–57). If the clock

frequency is 167 MHz, the half-clock period T/2 is:

T/2 = 1/(2* f )= 1 /(2*167 MHz) = 3 ns = 3000 ps

1.5-V

280

SSTL-2 Class I

150

190

230

SSTL-2 Class II

155

200

230

SSTL-18 Class I

180

240

260

HSTL-18 Class I

180

235

HSTL-15 Class I

205

220

Differential SSTL-2 Class I

150

190

230

Differential SSTL-2 Class II

155

200

230

Differential SSTL-18 Class I

180

240

260

Differential HSTL-18 Class I

180

235

Differential HSTL-15 Class I

205

220

LVDS

110

120

Simple RSDS

100

155

Mini LVDS

110

120

PCI

285

305

335

PCI-X

285

305

335

Notes to Table 5–57:

(1)

The DCD specification is characterized using the maximum drive strength

available for each I/O standard.

(2)

Numbers are applicable for commercial, industrial, and automotive devices.

Table 5–57. Maximum for DDIO Output on Row Pins with PLL in the Clock

Path

Notes (1), (2) (Part 2 of 2)

Row Pins with PLL in the Clock Path

Unit

EP2C8A Datasheet(PDF) 162 Page - Altera Corporation

EP2C8A Datasheet(HTML) 162 Page - Altera Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL