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DS2152L Datasheet(PDF) 75 Page - Dallas Semiconductor |
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DS2152L Datasheet(HTML) 75 Page - Dallas Semiconductor |
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75 / 94 page ![]() DS2152 75 of 93 DS2152 JITTER ATTENUATION Figure 14-4 15.0 TIMING DIAGRAMS RECEIVE SIDE D4 TIMING Figure 15-1 NOTES: 1. RSYNC in the frame mode (RCR2.4=0) and double-wide frame sync is not enabled (RCR2.5=0). 2. RSYNC in the frame mode (RCR2.4=0) and double-wide frame sync is enabled (RCR2.5=1). 3. RSYNC in the multiframe mode (RCR2.4=1). 4. RLINK data (Fs bits) is updated 1 bit prior to even frames and held for two frames. 5. RLINK and RLCLK are not synchronous with RSYNC when the receive side elastic store is enabled. |
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