DS2152L datasheet(78/94 Pages) DALLAS

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DS2152

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TRANSMIT SIDE D4 TIMING Figure 15-6

NOTES:

1. TSYNC in the frame mode (TCR2.3=0) and double-wide frame sync is not enabled (TCR2.4=0).

2. TSYNC in the frame mode (TCR2.3=0) and double-wide frame sync is enabled (TCR2.4=1).

3. TSYNC in the multiframe mode (TCR2.3=1).

4. TLINK data (Fs bits) is sampled during the F-bit position of even frames for insertion into the

outgoing T1 stream when enabled via TCR1.2.

5. TLINK and TLCLK are not synchronous with TSSYNC.

TRANSMIT SIDE TIMING Figure 15-7

NOTES:

1. TSYNC in the frame mode (TCR2.3=0) and double-wide frame sync is not enabled (TCR2.4=0).

2. TSYNC in the frame mode (TCR2.3=0) and double-wide frame sync is enabled (TCR2.4=1).

3. TSYNC in the multiframe mode (TCR2.3=1).

4. ZBTSI mode disabled (TCR2.5=0).

5. TLINK data (FDL bits) is sampled during the F-bit time of odd frame and inserted into the outgoing

T1 stream if enabled via TCR1.2.

6. ZBTSI mode is enabled (TCR2.5=1).

7. TLINK data (Z bits) is sampled during the F-bit time of frames 1, 5, 9, 13, 17, and 21 and inserted

into the outgoing stream if enabled via TCR1.2.

8. TLINK and TLCLK are not synchronous with TSSYNC.

DS2152L Datasheet(PDF) 78 Page - Dallas Semiconductor