INA210 datasheet(10/39 Pages) TI1

10 / 39 page

INA220

SBOS459D – JUNE 2009 – REVISED SEPTEMBER 2010

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Serial Interface

When reading from the INA220, the last value stored

in the register pointer by a write operation determines

The INA220 operates only as a slave device on the

which register is read during a read operation. To

Two-Wire bus and SMBus. Connections to the bus

change the register pointer for a read operation, a

are made via the open-drain I/O lines SDA and SCL.

new value must be written to the register pointer. This

The SDA and SCL pins feature integrated spike

write is accomplished by issuing a slave address byte

suppression filters and Schmitt triggers to minimize

with the R/W bit LOW, followed by the register pointer

the effects of input spikes and bus noise. The INA220

byte. No additional data are required. The master

supports the transmission protocol for fast (1kHz to

then generates a START condition and sends the

400kHz) and high-speed (1kHz to 3.4MHz) modes.

slave address byte with the R/W bit HIGH to initiate

All data bytes are transmitted most significant byte

the read command. The next byte is transmitted by

first.

the slave and is the most significant byte of the

WRITING TO/READING FROM THE INA220

followed by an Acknowledge from the master; then

the slave transmits the least significant byte. The

Accessing a particular register on the INA220 is

master acknowledges receipt of the data byte. The

accomplished by writing the appropriate value to the

master may terminate data transfer by generating a

Not-Acknowledge after receiving any data byte, or

registers and corresponding addresses. The value for

generating a START or STOP condition. If repeated

the register pointer as shown in Figure 17 is the first

reads from the same register are desired, it is not

byte transferred after the slave address byte with the

necessary to continually send the register pointer

R/W bit LOW. Every write operation to the INA220

bytes; the INA220 retains the register pointer value

requires a value for the register pointer.

until it is changed by the next write operation.

Writing to a register begins with the first byte

Figure 14 and Figure 15 show read and write

transmitted by the master. This byte is the slave

operation timing diagrams, respectively. Note that

address, with the R/W bit LOW. The INA220 then

acknowledges receipt of a valid address. The next

followed by the least significant byte. Figure 16

byte transmitted by the master is the address of the

shows the timing diagram for the SMBus Alert

response operation. Figure 17 illustrates a typical

address value updates the register pointer to the

desired register. The next two bytes are written to the

INA220 acknowledges receipt of each data byte. The

master may terminate data transfer by generating a

START or STOP condition.

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