DS80C400 datasheet(40/97 Pages) DALLAS

40 / 97 page

DS80C400 Network Microcontroller

40 of 97

TIMED-ACCESS PROTECTION

Selected SFR bits are critical to operation, making it desirable to protect them against an accidental write

operation. The timed-access procedure prevents errant behavior from accidentally altering bits that would seriously

affect microcontroller operation. The timed-access procedure requires that the write of a protected bit be

immediately preceded by the following two instructions:

MOV

0C7h, #0AAh

MOV

0C7h, #55h

Writing an AAh followed by a 55h to the timed access register (location C7h), opens a three-cycle window that

allows software to modify one of the protected bits. The protected bits are:

SFR

BIT(S)

NAME

FUNCTION

EXIF (91h)

EXIF.0

BGS

Bandgap Select

P4CNT (92h)

P4CNT.5–0

—

Port 4 Pin Configuration Control Bits

ACON (9Dh)

ACON.5

MROM

Merge ROM

—

ACON.4

BPME

Breakpoint Mode Enable

—

ACON.3

BROM

By-Pass ROM

—

ACON.2

Stack Address Mode

—

ACON.1–0

AM1–AM0

Address Mode Select Bits

P5CNT (A2h)

P5CNT.2–0

—

Port 5 Pin Configuration Control Bits

C0C (A3h)

C0C.3

CRST

CAN 0 Reset

P6CNT (B2h)

P6CNT.5–0

—

Port 6 Pin Configuration Control Bits

MCON (C6h)

MCON.7–6

IDM1–IDM0

Internal Memory Configuration Bits

—

MCON.5

CAN

CMA Data Memory Assignment

—

MCON.3–0

PDCE3–PDCE0

Program/Data-Chip Enables

COR (CEh)

COR.7

IRDACK

IRDA Clock-Output Enable

—

COR.4–3

C0BPR7–C0BPR6

CAN 0 Baud Rate Prescale Bits

—

COR.2–1

COD1–COD0

CAN Clock-Output Divide Bits

—

COR.0

CLKOE

CAN Clock-Output Enable

MCON1 (D6h)

MCON1.3–0

PDCE7–PDCE4

Program/Data Chip Enable

MCON2 (D7h)

MCON2.6–4

WPR2–WPR0

Write-Protect Range Bits

MCON2.3–0

WPE3–WPE0

Write-Protect Enable Bits

WDCON (D8h)

WDCON.6

POR

Power-On Reset Flag

—

WDCON.3

WDIF

Watchdog Interrupt Flag

—

WDCON.1

EWT

Watchdog Reset Enable

—

WDCON.0

RWT

Reset Watchdog Timer

EBS (E5h)

EBS.7

FPE

Flush Filter Failed-Packet Enable

—

EBS.4–0

BS4-BS0

Buffer Size Configuration Bits

MEMORY ARCHITECTURE

The DS80C400 incorporates four internal memory areas:

256 Bytes of scratchpad (or direct) RAM

8kB of SRAM for Ethernet MAC transmit/receive buffer memory

1kB of SRAM configurable as various combinations of data memory and stack memory

256 Bytes of RAM reserved for the CAN message centers

64kB embedded ROM firmware

Up to 16MB of external code memory can be addressed through a multiplexed or demultiplexed 22-bit address

bus/8-bit data bus through eight available chip enables. Up to 4MB of external data memory can be accessed over

the same address/data buses through peripheral-enable signals. The DS80C400 also permits a 16MB merged

program/data memory map.

DS80C400 Datasheet(PDF) 40 Page - Dallas Semiconductor

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