DS80C400 datasheet(52/97 Pages) DALLAS

52 / 97 page

DS80C400 Network Microcontroller

52 of 97

Each CSR register is documented as follows:

CSR Register:

MAC Control

00h

Bit Names:

BLE

—

HBD

—

DRO

OM[1:0]

—

LCC

DBF

DRTY

—

ASTP

BLOMT[1:0]

—

Reset State:

RA, Receive All. This bit overrides the flush-filter failed-packet function if that function has been enabled

(EBS.7 = 1).

0 = default frame handling (default)

1 = all error-free frames are received with packet filter bit set (= 1) in the receive status word

BLE, Big-/Little-Endian Mode

0 = data buffers are operated in little-endian mode (default)

1 = data buffers are operated in big-endian mode

HBD, Heart-Beat Disable. This bit is only useful in ENDEC mode and has no effect on MII mode operation.

0 = heart-beat signal quality-generator function enabled (default)

1 = heart-beat signal quality-generator function is disabled

PS, Port Select

0 = MII mode (default)

1 = ENDEC mode

DRO, Disable Receive Own. This bit should always be cleared to a logic 0 for full-duplex operation and any

loopback operating modes other than “normal mode.”

0 = MAC receives all packets given by the PHY (default)

1 = MAC disables reception of frames during frame transmission (TX_EN = 1)

OM[1:0], Loopback Operating Mode

00 = normal mode, no loopback (default)

01 = internal loopback through MII

10 = external loopback through PHY

11 = reserved

F, Full-Duplex Mode

0 = half-duplex mode (default)

1 = full-duplex mode

PM, Pass All Multicast

0 = multicast frames filtered according to current multicast filter mode (default)

1 = pass all multicast frames; filter-fail bit is reset (= 0) for all multicast frames received

PR, Promiscuous Mode

0 = promiscuous mode disabled

1 = promiscuous mode enabled (default)

DS80C400 Datasheet(PDF) 52 Page - Dallas Semiconductor

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