DS80C400 datasheet(47/97 Pages) DALLAS

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DS80C400 Network Microcontroller

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Table 9. Data Memory Cycle Stretch Values

APPROXIMATE

RD, WR PULSE WIDTH

(IN OSCILLATOR CLOCKS)

MD2

MD1

MD0

STRETCH

VALUE

MOVX

MACHINE

CYCLES

(4X/

2X = 1

CD1:0 = 00)

(4X/

2X = 0

CD1:0 = 00)

(4X/

2X = X

CD1:0 = 10)

(4X/

2X = X

CD1:0 = 11)

0 (Note 1)

0.5 tCLK

1 tCLK

2 tCLK

512 tCLK

1 (Note 2)

1 tCLK

2 tCLK

4 tCLK

1024 tCLK

2 tCLK

4 tCLK

8 tCLK

2048 tCLK

3 tCLK

6 tCLK

12 tCLK

3072 tCLK

4 tCLK

8 tCLK

16 tCLK

4096 tCLK

5 tCLK

10 tCLK

20 tCLK

5120 tCLK

6 tCLK

12 tCLK

24 tCLK

6144 tCLK

7 tCLK

14 tCLK

28 tCLK

7168 tCLK

Note 1: All internal MOVX operations execute at the 0 stretch setting.

Note 2: Default stretch setting for external MOVX operations following reset, but reset before execution of ROM startup code.

Internal MOVX SRAM

The DS80C400 contains 9kB of SRAM that is physically divided into a 1kB block and an 8kB block. The 1kB block

can be used to support the extended stack-pointer function or can be used as general-purpose MOVX data

memory. The 8kB block is used by the Ethernet MAC as frame-buffer memory for incoming or outgoing packet data

and can, at the same time, be accessed by the DS80C400 as MOVX data memory. While the MAC is in use,

special care should be taken by user software to prevent undesirable MOVX writes from corrupting frame-buffer

memory. The address mapping of the 1kB block and the 8kB block are governed by the internal data-memory

configuration bits (IDM1, IDM0) in the memory control register (MCON;C6h). Note that when the SA bit (ACON.2)

is set, 1kB of the MOVX data memory is accessed by the 10-bit expanded stack pointer. Changing the IDM1:0

configuration bits while SA = 1 does not disrupt the extended stack-pointer function. Internal MOVX memory

accesses do not generate

WR or RD strobes.

The DS80C400 contains an additional 256 Bytes of internal SRAM that is used to configure and operate the 15

CAN-controller message centers. The address location of this 256-Byte block is determined by the CAN data-

memory assignment bit (CMA) in the memory control register (MCON; C6h).

Table 10. Internal MOVX SRAM Configuration

IDM1

IDM0

CMA

8kB BLOCK

(MAC/MOVX DATA)

1kB BLOCK

(STACK/MOVX DATA)

256-BYTE

(CAN DATA MEMORY)

00E000h–00FFFFh

00DC00h–00DFFFh

00DB00h–00DBFFh

00E000h–00FFFFh

00DC00h–00DFFFh

FFDB00h–FFDBFFh

000000h–001FFFh

002000h–0023FFh

00DB00h–00DBFFh

000000h–001FFFh

002000h–0023FFh

FFDB00h–FFDBFFh

FFE000h–FFFFFFh

FFDC00h–FFDFFFh

00DB00h–00DBFFh

FFE000h–FFFFFFh

FFDC00h–FFDFFFh

FFDB00h–FFDBFFh

Extended Stack Pointer

The DS80C400 supports both the traditional 8-bit and an extended 10-bit stack pointer that improves the

performance of large programs written in high-level languages such as C. To enable the 10-bit stack pointer, set

the stack-address mode bit, SA (ACON.2). The bit is cleared following a reset, forcing the device to use an 8-bit

stack located in the scratchpad RAM area. When the SA bit is set, the device addresses up to 1kB of internal

MOVX memory for stack purposes. The 10-bit stack pointer address is generated by concatenating the lower two

bits of the extended stack pointer (ESP;9Bh) and the traditional 8051 stack pointer (SP;81h).

On-Chip Arithmetic Accelerator

An on-chip math accelerator allows the microcontroller to perform 32-bit and 16-bit multiplication, division, shifting,

and normalization using dedicated hardware. Math operations are performed by sequentially loading three special

registers. The mathematical operation is determined by the sequence in which three dedicated SFRs (MA, MB, and

MCNT0) are accessed, eliminating the need for a special step to choose the operation. The normalize function

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