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80960MC Datasheet(PDF) 8 Page - Intel Corporation

Part # 80960MC
Description  EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT
PDF  39 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

80960MC Datasheet(HTML) 8 Page - Intel Corporation

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80960MC
4
PRELIMINARY
Figure 2. Instruction Formats
Opcode
Displacement
Opcode
Reg/Lit
Reg
M
Displacement
Displacement
Control
Compare and
Branch
Register to
Register
Memory Access-
Short
Memory Access-
Long
Opcode
Reg
Reg/Lit
Modes
Ext’d Op
Reg/Lit
Opcode
Reg
Base
M
X
Offset
Opcode
Reg
Base
Mode
Scale
xx
Offset
1.1.1
Memory Space And Addressing Modes
The 80960MC allows each task (process) to address
a logical memory space of up to 4 Gbytes. Each
task’s address space is divided into four 1 Gbyte
regions and each region can be mapped to physical
addresses by zero, one, or two levels of page tables.
The region with the highest addresses (Region 3) is
common to all tasks.
In keeping with RISC design principles, the number
of addressing modes is minimal yet includes all
those necessary to ensure efficient execution of
high-level languages such as Ada, C, and Fortran.
Table 2 lists the memory accessing modes.
1.1.2
Data Types
The 80960MC recognizes the following data types:
Numeric:
• 8-, 16-, 32- and 64-bit ordinals
• 8-, 16-, 32- and 64-bit integers
• 32-, 64- and 80-bit real numbers
Non-Numeric:
•Bit
• Bit Field
• Triple Word (96 bits)
• Quad-Word (128 bits)
1.1.3
Large Register Set
The 80960MC programming environment includes a
large number of registers. 36 registers are available
at any time; this greatly reduces the number of
memory accesses required to perform algorithms,
which leads to greater instruction processing speed.
Two types of general-purpose registers are avail-
able: local and global. The 20 global registers
consist of sixteen 32-bit registers (G0 though G15)
and four 80-bit registers (FP0 through FP3). These
Table 2. Memory Addressing Modes
• 12-Bit Offset
• 32-Bit Offset
• Register-Indirect
• Register + 12-Bit Offset
• Register + 32-Bit Offset
• Register + (Index-Register x Scale-Factor)
• Register x Scale Factor + 32-Bit Displacement
• Register + (Index-Register x Scale-Factor) + 32-
Bit Displacement
• Scale-Factor is 1, 2, 4, 8 or 16



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