80960MC datasheet(5/39 Pages) INTEL

5 / 39 page

PRELIMINARY

80960MC

1.0

THE i960® MC PROCESSOR

The 80960MC, a member of Intel’s i960

® 32-bit

processor family, is ideally suited for embedded

applications. It includes a 512-byte instruction cache

and a built-in interrupt controller. The 80960MC has

a large register set, multiple parallel execution units

and a high-bandwidth burst bus. Using advanced

RISC technology, this processor is capable of

execution rates in excess of 9.4 million instructions

per second

*. The 80960MC is well-suited for a wide

range of applications including non-impact printers,

I/O control and

specialty

instrumentation.

The

embedded market includes applications as diverse

industrial

automation,

avionics,

image

processing, graphics and networking. These types of

applications require high integration, low power

consumption, quick interrupt response times and

* Relative to Digital Equipment Corporation’s VAX-11/780*

at 1 MIPS

high performance. Since time to market is critical,

embedded processors must be easy to use in both

hardware and software designs.

All members of the i960 processor family share a

common core architecture which utilizes RISC tech-

nology so that, except for special functions, the

family members are object-code compatible. Each

new processor in the family adds its own special set

of functions to the core to satisfy the needs of a

specific application or range of applications in the

embedded market.

The 80960MC includes an integrated Floating Point

Unit (FPU), a Memory Management Unit (MMU),

multitasking support, and multiprocessor support.

Two commercial members of the i960® family

provide similar features: the 80960KB processor with

integrated FPU and the 80960KA without floating-

point.

Figure 1. 80960MC Programming Environment

INSTRUCTION CACHE

INSTRUCTION

STREAM

FETCH

LOAD

STORE

SIXTEEN 32-BIT GLOBAL REGISTERS

g15

SIXTEEN 32-BIT LOCAL REGISTERS

FOUR 80-BIT FLOATING POINT REGISTERS

r15

CONTROL REGISTERS

INSTRUCTION

EXECUTION

INSTRUCTION

POINTER

ARITHMETIC

CONTROLS

PROCESS

CONTROLS

TRACE

CONTROLS

ARCHITECTURALLY

DEFINED

DATA STRUCTURES

FFFF FFFFH

0000 0000H

ADDRESS SPACE

PROCESSOR STATE

REGISTERS

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