80960MC datasheet(26/39 Pages) INTEL

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80960MC

PRELIMINARY

Figure 18. HOLD Timing

A4490-01

HOLDR

HOLDAR

Secondary

HOLD

HLDA

Primary

Delay of 5 ns Minimum

is Required

CLK2

CLK

HOLDR

HOLD

HLDA

HLDAR

T9h

T11h

T9h

T11h

T12

T6h

T12

T6h

2.9

Design Considerations

Input hold times can be disregarded by the designer

whenever the input is removed because a subse-

quent output from the processor is deasserted (e.g.,

DEN becomes deasserted).

In other words, whenever the processor generates

an output that indicates a transition into a subse-

quent state, the processor must have sampled any

inputs for the previous state.

Similarly, whenever the processor generates an

output that indicates a transition into a subsequent

state, any outputs that are specified to be three

stated in this new state are guaranteed to be three

stated.

3.0

MECHANICAL DATA

3.1

Packaging

The 80960MC is available in one package type: a

132-lead ceramic pin-grid array (PGA). Pins are

arranged 0.100 inch (2.54 mm) center-to-center, in a

14 by 14 matrix, three rows around (see Figure 20).

Dimensions for the PGA package type is given in the

Intel

Packaging handbook (Order #240800).

3.1.1

Pin Assignment

Figure 21 shows the view from the PGA bottom (pins

facing up). Table 8 and Table 9 list the function of

each PGA pin.

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