80960MC datasheet(12/39 Pages) INTEL

12 / 39 page

80960MC

PRELIMINARY

Second, a set of synchronization instructions help

maintain memory coherency. These instructions

permit several processors to modify memory at the

same time without inserting inaccuracies or ambigu-

ities into shared data structures.

The self-dispatching mechanism — in addition to

being used in single-processor systems — provides

the means to increase the performance of a system

merely by adding processors. Each processor can

either work on the same pool of tasks (sharing the

same queue with other processors) or can be

restricted to its own queue.

When processors perform system operation, they

synchronize themselves by using atomic operations

and sending special messages between each other.

In theory, changing the number of processors in a

system

does not

require

software

change.

Software

executes

correctly regardless

the

number of processors in the system; systems with

more processors simply execute faster.

1.1.13 Interrupt Handling

The 80960MC can be interrupted in two ways: by the

activation of one of four interrupt pins or by sending

a message on the processor’s data bus.

The 80960MC is unusual in that it automatically

handles interrupts on a priority basis and can keep

track of pending interrupts through its on-chip inter-

rupt controller. Two of the interrupt pins can be

configured to provide 8259A-style handshaking for

expansion beyond four interrupt lines.

An interrupt message is made up of a vector number

and an interrupt priority. When the interrupt priority is

greater than that of the currently running task, the

processor accepts the interrupt and uses the vector

as an index into the interrupt table. When the priority

of the interrupt message is below that of the current

task, the processor saves the information in a

section of the interrupt table reserved for pending

interrupts.

1.1.14 Debug Features

The

80960MC

has

built-in

debug

capabilities,

including two types of breakpoints and six trace

modes. Debug features are controlled by two

internal 32-bit registers: the Process-Controls Word

and the Trace-Controls Word. By setting bits in these

control words, a software debug monitor can closely

control how the processor responds during program

execution.

The 80960MC has both hardware and software

breakpoints. It provides two hardware breakpoint

registers

on-chip

which,

using

special

command, can be set to any value. When the

instruction pointer matches either breakpoint register

value, the breakpoint handling routine is automati-

cally called.

The 80960MC also provides software breakpoints

through the use of two instructions: MARK and

FMARK. These can be placed at any point in a

program and cause the processor to halt execution

at that point and call the breakpoint handling routine.

The breakpoint mechanism is easy to use and

provides a powerful debugging tool.

Tracing is available for instructions (single step

execution), calls and returns and branching. Each

trace type may be enabled separately by a special

debug instruction. In each case, the 80960MC

executes the instruction first and then calls a trace

handling routine (usually part of a software debug

monitor). Further program execution is halted until

the routine completes, at which time execution

resumes at the next instruction. The 80960MC’S

tracing mechanisms, implemented completely in

hardware, greatly simplify the task of software test

and debug.

1.1.15 Fault Detection

The 80960MC has an automatic mechanism to

handle faults. There are ten fault types include

floating point, trace and arithmetic faults. When the

processor detects a fault, it automatically calls the

appropriate fault handling routine and saves the

current instruction pointer and necessary state infor-

mation to make efficient recovery possible. The

processor posts diagnostic information on the type of

fault to a Fault Record. Like interrupt handling

routines, fault handling routines are usually written to

meet the needs of specific applications and are often

included as part of the operating system or kernel.

For each of the ten fault types, numerous subtypes

provide specific information about a fault. For

example, a floating point fault may have the subtype

set to an Overflow or Zero-Divide fault. The fault

handler can use this specific information to respond

correctly to the fault.

80960MC Datasheet(PDF) 12 Page - Intel Corporation

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