80960MC datasheet(16/39 Pages) INTEL

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80960MC

PRELIMINARY

FAILURE

O.D.

INITIALIZATION FAILURE indicates that the processor did not initialize correctly.

After RESET deasserts and before the first bus transaction begins, FAILURE

asserts while the processor performs a self-test. When the self-test completes

successfully, then FAILURE deasserts. The processor then performs a zero

checksum on the first eight words of memory. When it fails, FAILURE asserts for a

second time and remains asserted. When it passes, system initialization continues

and FAILURE remains deasserted.

IAC/INT0

LOCAL

PROCESSOR

NUMBER

INTERAGENT COMMUNICATION REQUEST/INTERRUPT 0 indicates an IAC

message or an interrupt is pending. The bus interrupt control register determines

how the signal is interpreted. To signal an interrupt or IAC request in a synchronous

system, this pin — as well as the other interrupt pins — must be enabled by being

deasserted for at least one bus cycle and then asserted for at least one additional

bus cycle. In an asynchronous system the pin must remain deasserted for at least

two bus cycles and then asserted for at least two more bus cycles.

LOCAL PROCESSOR NUMBER - this signal is interpreted differently during

system reset. When the signal is a high voltage level it indicates that this processor

is a primary bus master (local processor number = 0). When at a low voltage level it

indicates that this processor is a secondary bus master (local processor number

=1).

INT1

INTERRUPT 1, like INT0, provides direct interrupt signaling.

INT2/INTR

INTERRUPT2/INTERRUPT REQUEST: The interrupt control register determines

how this pin is interpreted. When INT2, it has the same interpretation as the INT0

and INT1 pins. When INTR, it is used to receive an interrupt request from an

external interrupt controller.

INT3/INTA

I/O

O.D.

INTERRUPT3/INTERRUPT ACKNOWLEDGE: The bus interrupt control register

determines how this pin is interpreted. When INT3, it has the same interpretation as

the INT0, INT1 and INT2 pins. When INTA, it is used as an output to control

interrupt-acknowledge transactions. The INTA output is latched on-chip and

remains valid during Td cycles; as an output, it is open-drain.

N.C.

N/A

NOT CONNECTED indicates pins should not be connected. Never connect any pin

marked N.C. as these pins may be reserved for factory use.

Table 5. 80960MC Pin Description: Support Signals (Sheet 2 of 2)

NAME

TYPE

DESCRIPTION

I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state

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