80960MC datasheet(14/39 Pages) INTEL

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80960MC

PRELIMINARY

ADS

O.D.

ADDRESS/DATA STATUS indicates an address state. ADS is asserted every Ta

state and deasserted during the following Td state. For a burst transaction, ADS is

asserted again every Td state where READY was asserted in the previous cycle.

W/R

O.D.

WRITE/READ specifies, during a Ta cycle, whether the operation is a write or read.

It is latched on-chip and remains valid during Td cycles.

DT/R

O.D.

DATA TRANSMIT / RECEIVE indicates the direction of data transfer to and from

the L-Bus. It is low during Ta and Td cycles for a read or interrupt acknowledgment;

it is high during Ta and Td cycles for a write. DT/R never changes state when DEN

is asserted.

DEN

O.D.

DATA ENABLE (active low) enables data transceivers. The processor asserts

DEN# during all Td and Tw states. The DEN# line is an open drain-output of the

80960MC.

READY

READY indicates that data on LAD lines can be sampled or removed. When

READY is not asserted during a Td cycle, the Td cycle is extended to the next cycle

by inserting a wait state (Tw) and ADS is not asserted in the next cycle.

LOCK

I/O

O.D.

BUS LOCK prevents bus masters from gaining control of the L-Bus during

Read/Modify/Write (RMW) cycles. The processor or any bus agent may assert

LOCK.

At the start of a RMW operation, the processor examines the LOCK pin. When the

pin is already asserted, the processor waits until it is not asserted. When the pin is

not asserted, the processor asserts LOCK during the Ta cycle of the read trans-

action. The processor deasserts LOCK in the Ta cycle of the write transaction.

During the time LOCK is asserted, a bus agent can perform a normal read or write

but not a RMW operation.

The processor also asserts LOCK during interrupt-acknowledge transactions.

Do not leave LOCK unconnected. It must be pulled high for the processor to

function properly.

BE3:0

O.D.

BYTE ENABLE LINES specify the data bytes (up to four) on the bus which are

used in the current bus cycle. BE3 corresponds to LAD31:24; BE0 corresponds to

LAD7:0.

The byte enables are provided in advance of data:

Byte enables asserted during Ta specify the bytes of the first data word.

Byte enables asserted during Td specify the bytes of the next data word, if any (the

word to be transmitted following the next assertion of READY).

Byte enables that occur during Td cycles that precede the last assertion of READY

are undefined. Byte enables are latched on-chip and remain constant from one Td

cycle to the next when READY is not asserted.

For reads, byte enables specify the byte(s) that the processor actually uses. L-Bus

agents are required to assert only adjacent byte enables (e.g., asserting just BE0

and BE2 is not permitted) and are required to assert at least one byte enable.

Address bits A0 and A1 can be decoded externally from the byte enables.

Table 4. 80960MC Pin Description: L-Bus Signals (Sheet 2 of 3)

NAME

TYPE

DESCRIPTION

I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state

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