80960MC datasheet(34/39 Pages) INTEL

Part #	80960MC

Description	EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT

PDF	39 Pages

Scroll/Zoom	100%

Manufacturer	INTEL [Intel Corporation]

Direct Link	http://www.intel.com

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34 / 39 page

80960MC

PRELIMINARY

4.0

WAVEFORMS

The following figures present waveforms for various transactions on the 80960MC’S local bus:

• Figure 23, Non-Burst Read and Write Transactions Without Wait States (pg. 30)

• Figure 24, Burst Read and Write Transaction Without Wait States (pg. 31)

• Figure 25, Burst Write Transaction with 2, 1, 1, 1 Wait States (pg. 32)

• Figure 26, Accesses Generated by Quad Word Read Bus Request, Misaligned Two Bytes from Quad Word

Boundary (1, 0, 0, 0 Wait States) (pg. 33)

• Figure 27, Interrupt Acknowledge Transaction (pg. 34)

• Figure 28, Bus Exchange Transaction (PBM = Primary Bus Master, SBM = Secondary Bus Master) (pg. 35)

Figure 23. Non-Burst Read and Write Transactions Without Wait States

CLK2

CLK

LAD31:0

ALE

ADS

BE3:0

W/R

DT/R

DEN

READY

80960MC Datasheet(PDF) 34 Page - Intel Corporation