80960MC datasheet(1/39 Pages) INTEL

Part #	80960MC

Description	EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT

PDF	39 Pages

Scroll/Zoom	100%

Manufacturer	INTEL [Intel Corporation]

Direct Link	http://www.intel.com

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1 / 39 page

September, 1997

Order Number: 273123-001

PRELIMINARY

80960MC

EMBEDDED 32-BIT MICROPROCESSOR

WITH INTEGRATED FLOATING-POINT UNIT

AND MEMORY MANAGEMENT UNIT

Figure 1. The 80960MC Processor’s Highly Parallel Architecture

Commercial

s High-Performance Embedded Architecture

— 25 MIPS Burst Execution at 25 MHz

— 9.4 MIPS* Sustained Execution at

25 MHz

s On-Chip Floating Point Unit

— Supports IEEE 754 Floating Point

Standard

— Full Transcendental Support

— Four 80-Bit Registers

— 13.6 Million Whetstones/s

(Single Precision) at 25 MHz

s 512-Byte On-Chip Instruction Cache

— Direct Mapped

— Parallel Load/Decode for Uncached

Instructions

s Multiple Register Sets

— Sixteen Global 32-Bit Registers

— Sixteen Local 32-Bit Registers

— Four Local Register Sets Stored

On-Chip (Sixteen 32-Bit Registers per

Set)

— Register Scoreboarding

s On-Chip Memory Management Unit

— 4 Gbyte Virtual Address Space per

Task

— 4 Kbyte Pages with Supervisor/User

Protection

s Built-in Interrupt Controller

— 32 Priority Levels

— 248 Vectors

— Supports M8259A

—3.4

µs Latency @ 25 MHz

s Easy to Use, High Bandwidth 32-Bit Bus

— 66.7 Mbytes/s Burst

— Up to 16 Bytes Transferred per Burst

s Multitasking and Multiprocessor Support

— Automatic Task dispatching

— Prioritized Task Queues

s Advanced Package Technology

— 132-Lead Ceramic Pin Grid Array

SIXTEEN

32-BIT GLOBAL

REGISTERS

64- BY 32-BIT

LOCAL

REGISTER

CACHE

32-BIT

INSTRUCTION

EXECUTION

UNIT

INSTRUCTION

FETCH UNIT

512-BYTE

INSTRUCTION

CACHE

INSTRUCTION

DECODER

MICRO-

INSTRUCTION

SEQUENCER

MICRO-

INSTRUCTION

ROM

32-BIT

BUS CONTROL

LOGIC

32-BIT

BURST

BUS

FOUR

80-BIT FP

REGISTERS

80-BIT

FPU

MMU

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