82374EB datasheet(156/208 Pages) INTEL

156 / 208 page

82374EB82374SB

ICW1 starts the initialization sequence during which the following automatically occur

a Following initialization an interrupt request (IRQ) input must make a low-to-high transition to generate an

interrupt

b The Interrupt Mask Register is cleared

c IRQ7 input is assigned priority 7

d The slave mode address is set to 7

e Special Mask Mode is cleared and Status Read is set to IRR

ICW2 is programmed to provide bits 73 of the interrupt vector that will be released onto the data bus by

the interrupt controller during an interrupt acknowledge A different base 73 is selected for each interrupt

controller Suggested values for a typical EISA system are listed in Table 26

ICW3 is programmed differently for CNTRL-1 and CNTRL-2 and has a different meaning for each control-

ler

For CNTRL-1 the master controller ICW3 is used to indicate which IRQx input line is used to cascade

CNTRL-2 the slave controller Within the ESC interrupt unit IRQ2 on CNTRL-1 is used to cascade the INTR

output of CNTRL-2 Consequently bit 2 of ICW3 on CNTRL-1 is set to a 1 and the other bits are set to 0’s

For CNTRL-2 ICW3 is the slave identification code used during an interrupt acknowledge cycle CNTRL-1

broadcasts a code to CNTRL-2 over three internal cascade lines if an IRQ x line from CNTRL-2 won the

priority arbitration on the master controller and was granted an interrupt acknowledge by the CPU CNTRL-2

compares this identification code to the value stored in ICW3 and if the code is equal to bits 20 of ICW3

CNTRL-2 assumes responsibility for broadcasting the interrupt vector during the second interrupt acknowl-

edge cycle pulse

ICW4 must be programmed on both controllers At the very least bit 0 must be set toa1to indicate that the

controllers are operating in an 80x86 system

2 Operation Command Words (OCWs) These are the command words which dynamically reprogram the

Interrupt Controller to operate in various interrupt modes

Any interrupt lines can be masked by writing an OCW1 A 1 written in any bit of this command word will

mask incoming interrupt requests on the corresponding IRQx line

OCW2 is used to control the rotation of interrupt priorities when operating in the rotating priority mode and

to control the End of Interrupt (EOI) function of the controller

OCW3 is used to set up reads of the ISR and IRR to enable or disable the Special Mask Mode (SMM) and

to set up the interrupt controller in polled interrupt mode

The OCWs can be written into the Interrupt Controller any time after initialization Table 26 shows an

example of typical values programmed by the BIOS at power-up for the ESC interrupt controller

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82374EB Datasheet(PDF) 156 Page - Intel Corporation