82374EB datasheet(154/208 Pages) INTEL

154 / 208 page

82374EB82374SB

Note that externally the interrupt acknowledge cycle sequence appears different than in a traditional discrete

82C59 implementation However the traditional interrupt acknowledge sequence is generated within the ESC

and it is an EISA compatible implementation

1 One or more of the Interrupt Request (IRQ x ) lines are raised high setting the corresponding IRR bit(s)

2 The Interrupt Controller evaluates these requests and sends an INTR to the CPU if appropriate

3 The CPU acknowledges the INTR and responds with an interrupt acknowledge cycle This cycle is translat-

ed into a PCI bus command This PCI command is broadcast over the PCI bus as a single cycle as opposed

to the two cycle method typically used

4 Upon receiving an interrupt acknowledge cycle from the CPU over the PCI the PCEB converts the single

cycle into an INTA

pulse to the ESC The ESC uses the INTA

pulse to generate the two cycles that the

internal 8259 pair can respond to with the expected interrupt vector The cycle conversion is performed by a

functional block in the ESC Interrupt Controller Unit The internally generated interrupt acknowledge cycle is

completed as soon as possible as the PCI bus is held in wait states until the interrupt vector data is

returned Each cycle appears as an interrupt acknowledge pulse on the INTA

pin of the cascaded inter-

rupt controllers These two pulses are not observable at the ESC periphery

5 Upon receiving the first internally generated interrupt acknowledge the highest priority ISR bit is set and the

corresponding IRR bit is reset The Interrupt Controller does not drive the Data Bus during this cycle On the

trailing edge of the first cycle pulse a slave identification code is broadcast by the master to the slave on a

private internal three bit wide bus The slave controller uses these bits to determine if it must respond with

an interrupt vector during the second INTA

cycle

6 Upon receiving the second internally generated interrupt acknowledge the Interrupt Controller releases an

8-bit pointer (the interrupt vector) onto the Data Bus where it is read by the CPU

7 This completes the interrupt cycle In the AEOI mode the ISR bit is reset at the end of the second interrupt

acknowledge cycle pulse Otherwise the ISR bit remains set until an appropriate EOI command is issued at

the end of the interrupt subroutine

If no interrupt request is present at step four of either sequence (ie the request was too short in duration) the

Interrupt Controller will issue an interrupt level 7

93 80x86 Mode

When initializing the control registers of the 82C59 an option exists in Initialization Control Word Four (ICW4)

to select either an 80x86 or an MSC-85 microprocessor based system The interrupt acknowledge cycle is

different in an MSC-85 based system than in the 80x86 based system the interrupt acknowledge takes three

INTA

pulses with the MSC-85 rather than the two pulses with the 80x86 The ESC is used only in an 80x86

based system You must program each interrupt controller’s ICW4 bit 0 to a ‘‘1’’ to indicate that the interrupt

controller is operating in an 80x86 based system This setting ensures proper operation during an interrupt

acknowledge

931 ESC INTERRUPT ACKNOWLEDGE CYCLE

As discussed the CPU generates an interrupt acknowledge cycle that is translated into a single PCI command

and broadcast across the PCI bus to the PCEB The PCEB pulses the INTA

signal to the ESC The ESC

Interrupt Unit translates the INTA

signal into the two INTA

pulses expected by the interrupt controller

subsystem The Interrupt Controller uses the first interrupt acknowledge cycle to internally freeze the state of

the interrupts for priority resolution The first controller (CNTRL-1) as a master issues a three bit interrupt

code on the cascade lines to CNTRL-2 (internal to the ESC) at the end of the INTA

pulse On this first cycle

the interrupt controller block does not issue any data to the processor and leaves its data bus buffers disabled

CNTRL-2 decodes the information on the cascade lines compares the code to the byte stored in Initialization

154

82374EB Datasheet(PDF) 154 Page - Intel Corporation

82374EB Datasheet(HTML) 154 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL