82374EB datasheet(155/208 Pages) INTEL

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82374EB82374SB

Command Word Three (ICW3) and determines if it will have to broadcast the interrupt vector during the

second interrupt acknowledge cycle On the second interrupt acknowledge cycle the master (CNTRL-1) or

slave (CNTRL-2) will send a byte of data to the processor with the acknowledged interrupt code composed as

follows

Table 25 Content of Interrupt Vector Byte for 80x86 System Mode

Interrupt

IRQ715

IRQ614

IRQ513

IRQ412

IRQ311

IRQ210

IRQ19

IRQ08

NOTE

T7 – T3 represent the interrupt vector address (refer Register Description section)

The byte of data released by the interrupt unit onto the data bus is referred to as the ‘‘interrupt vector’’ The

format for this data is illustrated on a per-interrupt basis in Table 25

94 Programming The Interrupt Controller

The Interrupt Controller accepts two types of command words generated by the CPU or bus master

1 Initialization Command Words (ICWs) Before normal operation can begin each Interrupt Controller in

the system must be initialized In the 82C59 this is a two to four byte sequence However for the ESC each

controller must be initialized with a four byte sequence This four byte sequence is required to configure the

interrupt controller correctly for the ESC implementation This implementation is EISA-compatible

The four initialization command words are referred to by their acronyms ICW1 ICW2 ICW3 and ICW4

The base address for each interrupt controller is a fixed location in the IO memory space at 0020h for

CNTRL-1 and at 00A0h for CNTRL-2

An IO write to the CNTRL-1 or CNTRL-2 base address with data bit 4 equal to 1 is interpreted as ICW1 For

ESC-based EISA systems three IO writes to ‘‘base address a 1’’ (021h for CNTRL-1 and 0A0h for

CNTRL-2) must follow the ICW1 The first write to ‘‘base address a 1’’ (021h0A0h) performs ICW2 the

second write performs ICW3 and the third write performs ICW4

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82374EB Datasheet(PDF) 155 Page - Intel Corporation