DD28F032SA datasheet(6/49 Pages) INTEL

6 / 49 page

DD28F032SA

The DD28F032SA provides user-selectable block

locking to protect code or data such as device

drivers,

PCMCIA

card

information,

ROM-

executable O/S or application code. Each block

has an associated nonvolatile lock-bit which

determines the lock status of the block. In

addition, the DD28F032SA has a master Write

Protect

(WP#)

which

prevents

any

modifications to memory blocks whose lock-bits

are set.

The DD28F032SA contains three types of Status

Registers to accomplish various functions:

• A Compatible Status Register (CSR) which is

100% compatible with the 28F008SA FlashFile

memory’s Status Register. This register, when

used alone, provides a straightforward upgrade

capability

the

DD28F032SA

from

28F008SA-based design.

• A Global Status Register (GSR) which informs

the system of Command Queue status, Page

Buffer status, and overall Write State Machine

(WSM) status.

• 64 Block Status Registers (BSRs) which

provide block-specific status information such

as the block lock-bit status.

The GSR and BSR memory maps for byte-wide

and word-wide modes are shown in Figures 4

and 5.

The DD28F032SA incorporates an open drain

RY/BY# output pin. This feature allows the user to

OR-tie many RY/BY# pins together in a multiple

memory configuration such as a Resident Flash

Array. Other configurations of the RY/BY# pin are

enabled via special CUI commands and are

described in detail in the

16-Mbit Flash Product

Family User’s Manual.

The DD28F032SA also incorporates three chip-

enable input pins, CE0#, CE1# and CE2#. The

active low combination of CE0# and CE1# controls

the first 28F016SA. The active low combination of

CE0# and CE2# controls the second 28F016SA.

The

BYTE#

allows

either

x16

read/programs to the DD28F032SA. BYTE# at

logic low selects 8-bit mode with address A0

selecting between low byte and high byte. On the

other hand, BYTE# at logic high enables 16-bit

operation with address A1 becoming the lowest

order address and address A0 is not used (don’t

care). A device block diagram is shown in Figure

The DD28F032SA is specified for a maximum

access time of 70 ns (tACC) at 5.0V operation

(4.75V to 5.25V) over the commercial temperature

range (0°C to +70°C). A corresponding maximum

access time of 150 ns at 3.3V (3.0V to 3.6V and

0°C to +70°C) is achieved for reduced power

consumption applications.

The DD28F032SA incorporates an Automatic

Power Saving (APS) feature which substantially

reduces the active current when the device is in

static

mode

operation

(addresses

not

switching).

A deep power-down mode of operation is invoked

when the RP# (called PWD# on the 28F008SA)

pin is driven low. This mode provides additional

write protection by acting as a device reset pin

during power transitions. In the deep power-down

state, the WSM is reset (any current operation will

abort) and the CSR, GSR and BSR registers are

cleared.

A CMOS standby mode of operation is enabled

when either CE0#, or both CE1# and CE2#,

transition high and RP# stays high with all input

control pins at CMOS levels.

2.0 DEVICE PINOUT

The DD28F032SA Standard 56-Lead Dual Die

TSOP Type I pinout configuration is shown in

Figure 2.

DD28F032SA Datasheet(PDF) 6 Page - Intel Corporation

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