IMC010FLSA datasheet(8/39 Pages) INTEL

8 / 39 page

SERIES 2 FLASH MEMORY CARDS

ADDRESS DECODE

Address decoding provides the decoding logic for

the 2 to 20 Device Chip Enables and the elements of

the Attribute Memory Plane REG

selects between

the Common Memory Plane (REG

VIH) and the

Attribute Memory Plane (REG

VIL)

NOTE

The Series 2 Card has

active address inputs A0 to

A24 implying that reading and writing to addresses

beyond 32 Megabytes causes wraparound Further-

more reads to illegal addresses (for example be-

tween 20 and 32 Meg on a 20 Megabyte card) re-

turns Default data (00FFH or FFFFH)

The 28F008SA devices storing data applications or

firmware

form the Common Memory Plane ac-

cessed individually or as device pairs Memory is lin-

early mapped in the Common Memory Plane Three

memory access modes are available when access-

ing the Common Memory Plane Byte-Wide Word

Wide and Odd-Byte modes

Additional decoding selects the hardwired PCMCIA

CIS

and

Component

Management

Registers

mapped in the Attribute Memory Plane beginning at

address 000000H

The 512 memory-mapped even-byte CMRs are lin-

early mapped beginning at address 4000H in the At-

tribute Memory Plane

DATA CONTROL

Data Control Logic selects the path and direction for

accessing the Common or Attribute Memory Plane

It controls any of the PCMCIA-defined Word-Wide

Byte-Wide or Odd-Byte modes for either reads or

writes to these areas As shown in Table 3 input

pins which determine these selections are REG

A0 through A24 WE

CE1

and CE2

PCMCIA specifications allow only even-byte access

to the Attribute Memory Plane

In Byte-Wide mode bytes contiguous in software ac-

tually alternate between two device blocks of a de-

vice pair Therefore erasure of one device block

erases every other contiguous byte In accordance

with the PCMCIA standard for memory configuration

the Series 2 Card does not support confining contig-

uous bytes within one flash device when in by-8

mode

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