| Electronic Components Datasheet Search |
|
IMC010FLSA Datasheet(PDF) 22 Page - Intel Corporation |
|
|
|||||||||||||||||||||||||||||
IMC010FLSA Datasheet(HTML) 22 Page - Intel Corporation |
|
22 / 39 page ![]() SERIES 2 FLASH MEMORY CARDS 290434 – 27 Bus Command x8 Mode x16 Mode Operation Write Suspend Data e B0H Data e B0B0H Erase Address e Desired Address e Desired Block to Erase Block Pair to Erase Suspend Suspend Read Status Register Status Register Data Toggle OE Data Toggle OE or CE1 or CE2 to (CE1 and CE2 ) update Status to update Status Register Register Standby Check SR Bit 7 Check SR Bit 7 and 15 1 e Ready 1 e Ready 0 e Busy 0 e Busy Standby Check SR Bit 6 Check SR Bit 6 and 14 1 e Suspended 1 e Suspended 0 e In Progress 0 e In Progress Write Rd Array Data e FFH Data e FFFFH Cmd Read Read Data Read Data until finished until finished Write Erase Data e D0H Data e D0D0H Resume Address e Valid Address e Valid Block Address Block Pair Address Figure 15 Erase SuspendResume Algorithm Allows Reads to Interrupt Erases POWER CONSUMPTION STANDBY MODE In most applications software will only be accessing one device pair at a time The Series 2 Card is de- fined to be in the standby mode when one device pair is in the Read Array Mode while the remaining devices are in the Deep-Sleep Mode The Series 2 Card’s CE1 and CE2 input signals must also be at VIH In standby mode much of the card’s circuitry is shut off substantially reducing power consump- tion Typical power consumption for a 20 Megabyte Series 2 card in standby mode is 65 mA SLEEP MODE Writing a ‘‘1’’ to the PWRDWN bit of the GLOBAL POWERDOWN REGISTER places all FlashFile Memory devices into a Deep-Sleep mode This dis- ables most of the 28F008SA’s circuitry and reduces current consumption to 02 mA per device Addition- ally when the host system pulls ASIC control logic high and latches all address and data lines (ie not toggling) the card’s total current draw is reduced to approximately 5 mA (CMOS input levels) for a 20 Megabyte card On writing a ‘‘0’’ to the PWRDWN bit (Global PowerDown Register) or any individual de- vice pair (Sleep Control Register) a Deep-Sleep mode recovery period must be allowed for 28F008SA device circuitry to power back on 22 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |