IMC010FLSA datasheet(17/39 Pages) INTEL

17 / 39 page

SERIES 2 FLASH MEMORY CARDS

COMMAND DEFINITIONS

Read Array (FFH)

Upon initial card power-up after exit from the Deep-

Sleep modes and whenever illegal commands are

given individual devices default to the Read Array

mode This mode is also entered by writing FFH into

the CUI In this mode microprocessor read cycles

retrieve array data Devices remain enabled for

reads until the CUI receives an alternate command

Once the internal WSM has started a block-erase or

data-write operation within a device that device will

not recognize the Read Array command until the

WSM has completed its operation (or the Erase Sus-

pend command is issued during erase)

Intelligent Identifier (90H)

After executing this command the intelligent identifi-

er values can be read Only address A0 of each de-

vice is used in this mode all other address inputs

are reserved and should be cleared to 0 (Manufac-

turer code e 89H for A0 e 0) (Device code e A2H

for A0 e 1) The device will remain in this mode

until the CUI receives another command

This information is useful by system software in de-

termining what type of flash memory device is con-

tained within the card and allows the correct match-

ing of device to write and erase algorithms System

software that fully utilizes the PCMCIA specification

will not use the intelligent identifier mode as this

data is available within the Card Information Struc-

ture (refer to section on PCMCIA Card Information

Structure)

Read Status Register (70H)

After writing this command a device read outputs

the contents of its Status Register regardless of the

address presented to that device The contents of

this register are latched on the falling edge of OE

CE1

(andor CE2 ) whichever occurs last in the

read cycle This prevents possible bus errors which

might occur if the contents of the Status Register

changed while reading its contents CE1

(and

CE2

for odd-byte or word access) or OE

must be

toggled with each subsequent status read or the

completion of a write or erase operation will not be

evident

This command is executable while the

WSM is operating however during a block-erase or

data-write operation reads from the device will auto-

matically return status register data Upon comple-

tion of that operation the device remains in the

Status Register read mode until the CUI receives

another command

The read Status Register command functions when

VPP e VPPL or VPPH

Clear Status Register (50H)

The Erase Status and Write Status bits may be set

to ‘‘1’’s by the WSM and can only be reset by the

Clear Status Register Command These bits indicate

various failure conditions By allowing system soft-

ware to control the resetting of these bits several

operations may be performed (such as cumulatively

writing several bytes or erasing multiple blocks in

sequence) The device’s Status Register may then

be polled to determine if an error occurred during

that sequence This adds flexibility to the way the

device may be used

Additionally the VPP Status bit (SR3) MUST be re-

set by system software (Clear Status Register com-

mand) before further block-erases are attempted

(after an error)

The Clear Status Register command functions when

VPP e VPPL or VPPH This command puts the device

in the Read Array mode

Write SetupWrite

A two-command sequence executes a data-write

operation After the system switches VPP to VPPH

the write setup command (40H) is written to the CUI

of the appropriate device followed by a second

write specifying the address and write data (latched

on the rising edge of WE ) The device’s WSM con-

trols the data-write and write verify algorithms inter-

nally After receiving the two-command write se-

quence the device automatically outputs Status

detects the completion of the write operation by an-

alyzing card-level or device-level indicators Card-

level indicators include the RDYBSY

pin and the

READY-BUSY STATUS REGISTER while device-

level indicators include the specific device’s Status

is valid while the write operation is active Upon

completion of the data-write sequence (see section

on Status Register) the device’s Status Register re-

flects the result of the write operation The device

remains in the Read Status Register mode until the

CUI receives an alternate command

IMC010FLSA Datasheet(PDF) 17 Page - Intel Corporation

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