IMC010FLSA datasheet(23/39 Pages) INTEL

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SERIES 2 FLASH MEMORY CARDS

SYSTEM DESIGN CONSIDERATIONS

POWER SUPPLY DECOUPLING

Flash memory power-switching characteristics re-

quire careful device decoupling System designers

are interested in three supply current issuesstand-

by active and transient current peaks produced by

rising and falling edges of CE1

and CE2

The

capacitive and inductive loads on the card and inter-

nal flash memory device pairs determine the magni-

tudes of these peaks

The Flash Memory Card features on-card ceramic

decoupling capacitors connected between VCC and

GND and between VPP1 VPP2 and GND to help

transient voltage peaks

On the host side the card connector should also

have a 47 mF electrolytic capacitor between VCC

and GND as well as between VPP1 VPP2 and GND

The bulk capacitors will overcome voltage slumps

caused by printed-circuit-board trace inductance

and will supply charge to the smaller capacitors as

needed

POWER UPDOWN PROTECTION

Each device in the Flash Memory Card is designed

to offer protection against accidental erasure or writ-

ing caused by spurious system-level signals that

may exist during power transitions The card will

power-up into the Read Array Mode

A system designer must guard against active writes

for VCC voltages above VLKO when VPP is active

Since both WE

and CE1

(andor CE2 ) must be

low for a command write driving either to VIH will

inhibit writes With its Command User Interface al-

teration of device contents only occurs after suc-

cessful completion of the two-step command se-

quences

While these precautions are sufficient for most appli-

cations an alternative approach would allow VCC to

reach its steady state value before raising VPP1

VPP2 above VCC a 20V In addition upon power-

ing-down VPP1 VPP2 should be below VCC a 20V

before lowering VCC

HOT INSERTIONREMOVAL

The capability to remove or insert PC cards while the

system is powered on (ie

hot insertionremoval)

requires careful design approaches on the system

and card levels To design for this capability consid-

er card overvoltage stress system power droop and

control line stability

A PCMCIAJEIDA specified socket properly se-

quences the power supplies to the flash memory

card via shorter and longer pins This assures that

hot insertion and removal will not result in card dam-

age or data loss

PCMCIA CARD INFORMATION

STRUCTURE

The Card Information Structure (CIS) starts at ad-

dress zero of the card’s Attribute Memory Plane It

contains a variable-length chain of data blocks (tu-

ples) that conform to a basic format as shown in

Table 5 This section describes each tuple contained

within the Series 2 Flash Memory Card

The Device Information Tuple

This tuple (CISTPL

DEV e 01H) contains informa-

tion pertaining to the card’s speed and size The Se-

ries 2 Card is offered with a 150 nanosecond access

time Card sizes range between 2 and 20 Mega-

bytes

Table 5 Tuple Format

Bytes

Data

Tuple Code CISTPL

xxx The tuple code 0FFH indicates no more tuples in the list

Tuple Link TPL

LlNK Link to the next tuple in the list This can be viewed as the number of

additional bytes in tuple excluding this byte If the link field is zero the tuple body is empty If the

link field contains 0FFH this tuple is the last tuple in the list

2bn

Bytes specific to this tuple

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