IMC010FLSA datasheet(24/39 Pages) INTEL

24 / 39 page

SERIES 2 FLASH MEMORY CARDS

The Device Geometry Tuple

This tuple (CISTPL

DEVlCEGEO e 1EH) is con-

ceptually similar to a DOS disk geometry tuple

(CISTPL

GEOMETRY) except it is not a format-

dependent property this deals with the fixed archi-

tecture of the memory device(s)

Fields are defined as follows

DGTPL BUS

Value e n where system bus width

2(nb1) bytes N e 2 for standard PCMClA Re-

lease 1020 cards

DGTPL EBS

Value e n where the memory array’s

physical memory segments have a minimum erase

block

size

2(nb1)

address

increments

DGTPL

BUS-wide accesses

DGTPL RBS

Value e n where the memory ar-

ray’s physical memory segments have a minimum

read block size of 2(nb1) address increments of

DGTPL

BUS-wide accesses

DGTPL WBS

Value e n where the memory ar-

ray’s physical memory segments have a minimum

write block size of 2(nb1) address increments of

DGTPL

BUS-wide accesses

DGTPL PART

Value e n where the memory ar-

ray’s physical memory segments can have partitions

subdividing the arrays in minimum granularity of

2(nb1) number of erase blocks

FL DEVICE INTERLEAVE

Value e n where card

architectures employ a multiple of 2(nb1) times inter-

leaving of the entire memory arrays with the above

characteristics Non-interleaved cards have values

n e 1

Jedec Programming

Information Tuple

This tuple (CISTPL

JEDEC e 18H) contains the

Intel

manufacturing

identifier

(89H)

and

the

28F008SA device ID (A2H)

Level 1 VersionProduct

Information Tuple

This tuple (CISTPL

VERI e 15H) contains Level-1-

version compliance and card-manufacturer informa-

tion Fields are described as follows

TPLLV1 MAJOR

Major version number e 04H

TPLLV1 MINOR

Minor version number e 01H for

release 20

TPLLV1 INFO

Name of manufacturer e intel

Name of product

SERIES2-‘‘Card size’’

Card type

Speed

150 ns or 200 ns

REGBASE 4000H

Test Codes

DBBDRELP

Legalities

Corporation 1991

The Configurable Card Tuple

This tuple (ClSTPL

CONF e 1AH) describes the

interface supported by the card and the locations of

the Card Configuration Registers and the Card Con-

figuration Table

Fields are described as follows

TPCC SZ

Size of fields byte e 01H

TPCC LAST

Index number of the last entry in the

Card Configuration Table e 00H

TPCC RADR

Configuration Registers Base Ad-

dress in Reg Space e 4000H

TPCC

RMSK

Configuration

Registers

Present

Mask e 03H

The End-Of-List Tuple

The end-of-list tuple (CISTPL

END e FFH) marks

the end of a tuple chain Upon encountering this tu-

ple continue tuple processing as if a long-link to ad-

dress 0 of common memory space were encoun-

tered

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