Data Sheet S10299EJ4V0DS00

36

Figure 7–1. Controlling LCD Drive Voltage

Output port

µPD16434

CPU

Remark The power fed to the CPU and the

µ PD16434 must be from the same source.

(2) Clearing standby mode by RESET signal

For a system for which only the contents of the data memory need be held when the standby mode is cleared,

the RESET signal can be used to clear the standby mode.

When using the RESET signal for clearing the standby mode, set the RESET signal to high after the standby

mode is initiated (this can be checked by determining whether the /BUSY is set to high), then set the RESET signal

to low when clearing the standby mode. While the RESET signal is high, the LCD drive voltage becomes the same

as when it is in the reset operation, and no voltage is applied to the LCD. However, unlike normal reset operation,

the contents of the data memory will not become undefined by the RESET signal. The data which existed before

entering the standby mode is retained, and it can be used after clearing the standby mode. In a system which uses

this method, the current path control by the RESET signal shown in Figure5–5 can be used.

7.2 Stopping Clock Supply and Retaining Data at Low Voltage in Standby Mode

In the standby mode, only the data memory contents can be retained at a reduced voltage level. In this case, the

power consumption can be further reduced by stopping the CLOCK supply to the

µ PD16434. When stopping the

CLOCK supply to the

µ PD16434 in the standby mode, check that the µ PD16434 is in the standby mode (check that

the /BUSY signal is high, after executing the STOP command), set the RESET signal to high, then stop the CLOCK

supply to the

µ PD16434 after the specified time period.